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Visitor o.progin
Visitor
1,510 Views
Registered: ‎12-19-2017

Adding a DMA to a PCIe design

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Hi everyone,

 

I'm working on a project with a Zynq 7100 on a Mini-ITX board from Avnet. I'm currently working on Vivado 2016.4 and  Petalinux 2016.4

 

I've successfully connected a 4x USB to PCIe extension board to my Zynq based on an example design proposed by Avnet. I'm now able to connect and use USB device from my Linux system (Kernel version 4.6.0)

 

My problem:

I'm now trying to add a DMA to my existing design to use the PL for other operation. As presented in the block design below:

Block_design.png

The address mapping for this design are:

Address_mapping.png

 

But by doing so, I'm now getting the following error while booting:

 

xilinx-vdma 40400000.dma: Xilinx AXI VDMA Engine Driver Probed!!
e0001000.serial: ttyPS0 at MMIO 0xe0001000 (irq = 144, base_baud = 3125000) is a xuartps
random: nonblocking pool is initialized
���k�𬽱��[ttyPS0] enabled
console [ttyPS0] enabled
bootconsole [earlycon0] disabled
bootconsole [earlycon0] disabled
xdevcfg f8007000.devcfg: ioremap 0xf8007000 to f087e000
[drm] Initialized drm 1.1.0 20060810
irq 166: nobody cared (try booting with the "irqpoll" option)
CPU: 0 PID: 0 Comm: swapper/0 Not tainted 4.6.0-xilinx #1
Hardware name: Xilinx Zynq Platform
[<c010e48c>] (unwind_backtrace) from [<c010a6b0>] (show_stack+0x10/0x14)
[<c010a6b0>] (show_stack) from [<c02d05b4>] (dump_stack+0x80/0x9c)
[<c02d05b4>] (dump_stack) from [<c0153dc0>] (__report_bad_irq+0x24/0xc0)
[<c0153dc0>] (__report_bad_irq) from [<c01540c8>] (note_interrupt+0x1e4/0x28c)
[<c01540c8>] (note_interrupt) from [<c0151d1c>] (handle_irq_event_percpu+0xd4/0xe4)
[<c0151d1c>] (handle_irq_event_percpu) from [<c0151d64>] (handle_irq_event+0x38/0x5c)
[<c0151d64>] (handle_irq_event) from [<c0154b70>] (handle_fasteoi_irq+0xa8/0x124)
[<c0154b70>] (handle_fasteoi_irq) from [<c0151478>] (generic_handle_irq+0x18/0x28)
[<c0151478>] (generic_handle_irq) from [<c015174c>] (__handle_domain_irq+0x8c/0xb4)
[<c015174c>] (__handle_domain_irq) from [<c01013dc>] (gic_handle_irq+0x50/0x90)
[<c01013dc>] (gic_handle_irq) from [<c010b094>] (__irq_svc+0x54/0x90)
Exception stack(0xc0a01e90 to 0xc0a01ed8)
1e80:                                     00000000 00200000 00000000 00000000
1ea0: c0a00000 00000000 00000082 c0a3aa00 0000000a c0931a30 00000000 c0a01ee0
1ec0: 00000001 c0a01ee0 c011e784 c011e428 60000113 ffffffff
brd: module loaded
[<c010b094>] (__irq_svc) from [<c011e428>] (__do_softirq+0x68/0x1b0)
[<c011e428>] (__do_softirq) from [<c011e784>] (irq_exit+0x58/0xbc)
[<c011e784>] (irq_exit) from [<c0151750>] (__handle_domain_irq+0x90/0xb4)
[<c0151750>] (__handle_domain_irq) from [<c01013dc>] (gic_handle_irq+0x50/0x90)
[<c01013dc>] (gic_handle_irq) from [<c010b094>] (__irq_svc+0x54/0x90)
Exception stack(0xc0a01f60 to 0xc0a01fa8)
1f60: 00000001 00000000 00000000 c0116460 00000000 c0a00000 00000000 c0a01fb8
1f80: efffc1c0 c0931a30 00000000 00000000 2ee96000 c0a01fb0 c0107978 c010797c
1fa0: 60000013 ffffffff
[<c010b094>] (__irq_svc) from [<c010797c>] (arch_cpu_idle+0x2c/0x38)
[<c010797c>] (arch_cpu_idle) from [<c014a1f8>] (cpu_startup_entry+0x120/0x1d0)
loop: module loaded
[<c014a1f8>] (cpu_startup_entry) from [<c0900bbc>] (start_kernel+0x2ec/0x34c)
[<c0900bbc>] (start_kernel) from [<0000807c>] (0x807c)
handlers:
[<c032bce8>] xilinx_dma_irq_handler
Disabling IRQ #166

 

When doing a cat /proc/interrupts I can see that irq 166 is attached to the DMA controller more precisely it is the S2MM irq and that there is 100000 interruptions !

165:          0          0     GIC-0  90 Level     xilinx-dma-controller
166:     100000          0     GIC-0  89 Level     xilinx-dma-controller
167:          0          0     GIC-0  91 Level     xilinx-pcie
171:          0          0  Xilinx PCIe MSI   0 Edge      PCIe PME
176:          0          0  Xilinx PCIe MSI   5 Edge      xhci_hcd
177:          0          0  Xilinx PCIe MSI   6 Edge      xhci_hcd
178:          0          0  Xilinx PCIe MSI   7 Edge      xhci_hcd
179:          0          0  Xilinx PCIe MSI   8 Edge      xhci_hcd
180:          0          0  Xilinx PCIe MSI   9 Edge      xhci_hcd
181:          0          0  Xilinx PCIe MSI  10 Edge      xhci_hcd
182:          0          0  Xilinx PCIe MSI  11 Edge      xhci_hcd
183:          0          0  Xilinx PCIe MSI  12 Edge      xhci_hcd
184:          0          0  Xilinx PCIe MSI  13 Edge      xhci_hcd
185:          0          0  Xilinx PCIe MSI  14 Edge      xhci_hcd
186:          0          0  Xilinx PCIe MSI  15 Edge      xhci_hcd
187:          0          0  Xilinx PCIe MSI  16 Edge      xhci_hcd

 

If I try to connect a device to my USB to PCIe board, it does not get detected anymore.

At the same time if I write a small code trying to use the DMA with some mmap() I'm able to use the DMA to transfer data from one address to another since I disconnect interrupts.

 

Finally, if I disconnect the AXI-PCIe IP from my design and keep only the DMA, then I don't have any error while booting.

 

So I'm really confused about what is going on and I would be glade if someone could enlighten me on what I'm doing wrong.

 

Please find attached my pl.dtsi and and a copy of dmesg

 

Thanks a lot for your help

Best Regards

 

Olivier

 

 

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1 Solution

Accepted Solutions
Visitor o.progin
Visitor
1,445 Views
Registered: ‎12-19-2017

Re: Adding a DMA to a PCIe design

Jump to solution

Hi everyone,

 

I've finally been able to solve my problem so here is what I've made.

 

Instead of starting my project with the Avnet PCIe reference design, I made it from scratch with the board definition file and constraint file downloaded from the zedboard website http://zedboard.org/support/documentation/2056

 

My thought were that the issue was related to reset and clock signal used in my original design. I ended up with the attached design were all my issues are gone and everything works fine ;)

View solution in original post

PCIe_DMA_Design.png
3 Replies
Moderator
Moderator
1,347 Views
Registered: ‎02-16-2010

Re: Adding a DMA to a PCIe design

Jump to solution
Have you got any solution to this issue?

I have one question. The block diagram shows AXI-DMA IP but the error message shows a VDMA driver.

Are you referring to the following link related to the driver?
http://www.wiki.xilinx.com/DMA+Drivers+-+Soft+IPs

Check the device tree information specified for different types of DMA.
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Visitor o.progin
Visitor
1,294 Views
Registered: ‎12-19-2017

Re: Adding a DMA to a PCIe design

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Hi Venkata,

 

no I was not able to find a solution for my problem.

 

As described in the chang log at the bottom of the page in the link you've provided, since the 2016.3 version the three DMA drivers where merged into a single one called VDMA driver

"2016.3
Summary:

  • Mainlined the driver
  • Fixed the issues as per the commit ID
  • Deleted the AXI DMA/CDMA driver and Merged the AXI DMA/CDMA code with the VDMA driver
  • Merged all the 3 DMA's drivers into a single driver"

 

What I really don't get with my problem is the fact that if the AXI-PCIe block is disconnected from the block design, the DMA works just fine and there is no error while booting but once the AXI_PCIe is connected, this append.

 

Olivier

0 Kudos
Visitor o.progin
Visitor
1,446 Views
Registered: ‎12-19-2017

Re: Adding a DMA to a PCIe design

Jump to solution

Hi everyone,

 

I've finally been able to solve my problem so here is what I've made.

 

Instead of starting my project with the Avnet PCIe reference design, I made it from scratch with the board definition file and constraint file downloaded from the zedboard website http://zedboard.org/support/documentation/2056

 

My thought were that the issue was related to reset and clock signal used in my original design. I ended up with the attached design were all my issues are gone and everything works fine ;)

View solution in original post

PCIe_DMA_Design.png