03-25-2021 02:13 AM - edited 03-25-2021 02:18 AM
I want to use PCIe communication btw Alveo u200 and host using Vivado.
I just open example design of PCIe IP, but after that I don't know what to do.
Could you let me know how to do after this stage or some references?
And should I remove xocl or xrt for using PCIe at vivado?
Env: vivado 2020.1, alveo u200, ultrascale+ Integated Block (PCIE4)
P.S. I can't use Vitis because our project have to revise MIG
03-25-2021 09:24 PM
Hi @candycrush ,
You could configure PCIe IP and generate example design from that IP.
This will open up new project and generate bitstream. Later, program U200 with this bitfile and do lspci in your host machine on which the U200 is plugged in to PCIe edge connector slot.
03-26-2021 12:05 AM
03-26-2021 12:07 AM
03-28-2021 09:55 PM
Thanks for reply @aforencich !
Umm... I'm not sure what I'm trying to do is any of the kinds you mentioned.
Because I don't know about what things you mentioned are.. sorry.
More specifically, what I want to do is
I think my flow is very similar with NPU or Vitis.
Otherwise, I just want to transfer data from host to kernel directly (something like streaming?)