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candycrush
Contributor
Contributor
358 Views
Registered: ‎11-28-2018

Alveo pcie communication at "Vivado"

Hello, all

I want to use PCIe communication btw Alveo u200 and host using Vivado.

I just open example design of PCIe IP, but after that I don't know what to do.

Could you let me know how to do after this stage or some references?

And should I remove xocl or xrt for using PCIe at vivado?

 

Env: vivado 2020.1, alveo u200, ultrascale+ Integated Block (PCIE4)

P.S. I can't use Vitis because our project have to revise MIG

Thank you!

 

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aforencich
Explorer
Explorer
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Registered: ‎08-14-2013

Can you provide any more details on exactly what you want to do in terms of communicating with the card?

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pvenugo
Moderator
Moderator
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Registered: ‎07-31-2012

Hi @candycrush ,

You could configure PCIe IP and generate example design from that IP.

This will open up new project and generate bitstream. Later, program U200 with this bitfile and do lspci in your host machine on which the U200 is plugged in to PCIe edge connector slot.

 

Regards

Praveen


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candycrush
Contributor
Contributor
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Registered: ‎11-28-2018

Hi, @aforencich 

First, I just want to test PCIe connection using xillybus.

What I really want to do is passing packet list using PCIe to Alveo u200.

 

Thanks for replying!

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candycrush
Contributor
Contributor
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Registered: ‎11-28-2018

Hi, @pvenugo 

Thanks for reply!

I will try that.

Could you let me know how to do after that step you mentioned?

I mean how to communicate using PCIe btw host and FPGA

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aforencich
Explorer
Explorer
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Registered: ‎08-14-2013

Passing packet list?  So like packet DMA?  For networking via the kernel stack?  DPDK?  Or directly from an application?

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candycrush
Contributor
Contributor
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Registered: ‎11-28-2018

Thanks for reply @aforencich !

Umm... I'm not sure what I'm trying to do is any of the kinds you mentioned.

Because I don't know about what things you mentioned are.. sorry.

 

More specifically, what I want to do is

  1. Transfer data (256bit * N) from host to FPGA's memory
  2. After storing data, transfer start signal from host to kernel
  3. Kernel read data from memory
  4. Kernel Operation
  5. Kernel write data to memory
  6. After kernel op ends, read data from fpga to host.

I think my flow is very similar with NPU or  Vitis.

Otherwise, I just want to transfer data from host to kernel directly (something like streaming?)

 

Thanks!

 

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