Highly appreciate for any comments and suggestions.
I have a custom board using xc5vlx50t device configured as X1 lane, the endpoint plus core generated is 1.9.4 from ise 10.1.03. I hooked up the custom pcb to my pc and used pcitree to verify the basic operation of the core, the project was built with the sample design generated together with the core. After power up, the pcie core was successfully detected by the pcitree, and the basic rea/write/memory test in pcitree going very well, after playing a while, I scoped the cfg_dstatus output and found that the bits for correctable error detected and unsupported request detected were set high.
my question is, is it the normal situation that these bits being set ? or it implies that my custom pcb has something wrong, like too much noise, etc?