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Registered: ‎09-21-2018

Artix-7 PCIE Unroutable Placement

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Overview

I have a very simple block design (as shown in image attached) that instantiates a DMA/Bridge Subsystem for PCIe. This interfaces with an AXI Interconnect with only one peripheral for now, a Block Memory controller & generator. A utility buffer is configured as an IBUFDSGTE for the PCIE_REFCLK input. I have a set of pin constraints (shown in attached image) that I must follow. The pin constraints are all valid and correspond to Quad 116.

edit: Using part xc7a200tffg1156-2

 

Problem

I get the following error: [Place 30-511]: Unroutable Placement! A GTPE_COMMON / GTPE CHANNEL clock component pair is not placed in a routable site pair. The GTPE_COMMON component can use the dedicated path between the GTPE_COMMON and the GTPE_CHANNEL if both are placed in the same clock region. <continued...>

What is this actually telling me? The pin constraints that I am using place all MGT elements within the same quad, so is it trying to place it at the  PCIe Block Location: X0Y0 (as defined in the XDMA IP) and overriding my pin constraints? If so, the XDMA IP only gives X0Y0 as an option. How do I get around this error to get a valid placement?

Any help will be greatly appreciated.

pcie_test.png
pin_constraints.png
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Xilinx Employee
Xilinx Employee
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Registered: ‎10-19-2011

Hi @jacob.cleveland ,

the channel x1y4 that you select is a valid transceiver site that is true.

What you missed moving is the location constraint for the COMMON. This is still on x0y1 I guess as that is the default location. You will need to move this to x1y1. The constraints for TXP/TXN and RXP/RXN will just move the CHANNEL primitive.

Please be aware that the location you chose is on the opposite side of the device compared to the default location. See that you meet timing with this as the PCIe hard block does not move.

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Xilinx Employee
Xilinx Employee
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Registered: ‎10-19-2011

Hi @jacob.cleveland ,

the channel x1y4 that you select is a valid transceiver site that is true.

What you missed moving is the location constraint for the COMMON. This is still on x0y1 I guess as that is the default location. You will need to move this to x1y1. The constraints for TXP/TXN and RXP/RXN will just move the CHANNEL primitive.

Please be aware that the location you chose is on the opposite side of the device compared to the default location. See that you meet timing with this as the PCIe hard block does not move.

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Registered: ‎09-21-2018

Thank you, that clears things up a lot. Am I forced to use the Advanced Mode, Include Shared Logic (Transceiver GT_COMMON) in example design option when generating the XDMA IP, or is there another way to accomplish constraining the COMMON? I'd rather not have to write or instantiate all the necessary primitives by hand if I don't have to.

pcie_debug.PNG
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Xilinx Employee
Xilinx Employee
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Registered: ‎10-19-2011

Hi @jacob.cleveland ,

that should not be necessary. You could use a hierarchical assignment like this

set_property LOC GTM_DUAL_X0Y0 [get_cells -hierarchical -filter {NAME =~ *dual0/gtm_dual_inst}]

Of course you need to adjust to the GTP COMMON name and location

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Registered: ‎09-21-2018

Thanks eschidl! Just for reference, I was able to get a valid placement by adding the following constraint: set_property LOC GTPE2_COMMON_X1Y1 [get_cells -hierarchical -filter {NAME=~*gtpe2_common_i}]

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Explorer
Explorer
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Registered: ‎08-14-2013
I think if you switch the wizard from "basic" to "advanced", it gives you control over the transceiver sites. Changing that setting and then adjusting the transceiver site setting to match the pin configuration may be an alternative solution that doesn't require any additional constraints.
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