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Visitor
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Registered: ‎05-23-2018

Artix-7 SBG484 7-Series Integrated Block for PCI Express core support in ISE14.7

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Does 7 Series Integrated Block for PCI Express core in ISE14.7 support the Artix-7 SBG484 (XC7A200T-2SBG484) using the workaround suggested by the AR#57823 for Vivado2013.1 (and more recent tools) described below?

 

AR#57823:

The current 7 Series Integrated Block for PCI Express core release version v2.2 cannot be generated in Vivado for the Artix-7 SBG484 device.

This is a known issue to be fixed in a future release of the core.

As a work-around, generate the core for FBG484 and use it on the SBG484 device.

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Visitor
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Registered: ‎05-23-2018

Internal Xilinx experts answered to a ticket we posted:

“The core availability of the SBG484 package is a known issue for ISE and can be worked around by selecting the FGB484 package when building the IP, then importing into an SBG project. You need to check the pinout in both the devices and update the LOC constraints to suit SBG484.”

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Moderator
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Registered: ‎02-16-2010

Hi @csmxilinx2 ,

The issue you mentioned may not have fixed in ISE14.7. Have you tried the workaround mentioned in the AR?

Is it possible for you to use Vivado?

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Visitor
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Registered: ‎05-23-2018

Hello Venkata,

thank you for your reply.

I haven't tried the workaround yet but I would prefer not to have bad surprise if it doesn't work (i.e. if a hidden issue remains even if the core generation is successful). Implementing a PCI express in hardware has a certain cost and the feasability is my priority now. In a past project the Artix-7 SBG484 was in use and I would like to reuse the hardware block without changing the FPGA package.

Using Vivado is right now off the subject as we haven't started the portability of our designs for developpment tools above ISE14.7.

Let's hope that we can get the confirmation, that's mandatory, I can't just give a try.

Kind Regards.

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Visitor
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Registered: ‎05-23-2018

Internal Xilinx experts answered to a ticket we posted:

“The core availability of the SBG484 package is a known issue for ISE and can be worked around by selecting the FGB484 package when building the IP, then importing into an SBG project. You need to check the pinout in both the devices and update the LOC constraints to suit SBG484.”

View solution in original post

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