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Explorer
Explorer
897 Views
Registered: ‎01-23-2018

[BAR] Access

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Hi,

 

 

the following question is simple and I just want to be sure that I'm not misunderstanding. As you can see in the attached image this question is related with PCIe BAR configuration. In the image we can see how the AXI-Lite interface is enabled, so the question is pretty simple the field "Value" with value FFFF_FFFF_FFF0_0004 is the address where I will have to write from the host to access to that interface? I just want to use some writes as "special" so I don't want them to go to memory as main AXI interface does.

 

 

Regards,

 

Joel

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Moderator
Moderator
1,079 Views
Registered: ‎02-16-2010

Re: [BAR] Access

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In case of using Xilinx drivers I don't have to know the address, am I wrong?

Ans: You are not wrong

 

In case of using my own driver I should look into configuration space to be able to see how to communicate with AXI-Lite and how to communicate with AXI DMA because they will have to be accessed in different ways, am I wrong? 

Ans: You are not wrong

 

To read configuration space, you will need to use Type 0 Configuration Read Request

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5 Replies
Moderator
Moderator
873 Views
Registered: ‎02-16-2010

Re: [BAR] Access

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the screenshot is not attached. Can you attach it?
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Explorer
Explorer
869 Views
Registered: ‎01-23-2018

Re: [BAR] Access

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Dear @venkata,

 

sorry I attach it here.

 

 

Regards,

 

Joel

pcieBAR.JPG
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Moderator
Moderator
867 Views
Registered: ‎02-16-2010

Re: [BAR] Access

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You have to read configuration space header to know the BAR address map location after the enumeration is completed.
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Explorer
Explorer
833 Views
Registered: ‎01-23-2018

Re: [BAR] Access

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Hi @venkata,

 

 

thanks for helping. I've been reading again the Xilinx drivers documentation and I saw the information in the attached image, so I understand that in case of using Xilinx drivers I don't have to know the address, am I wrong? In case of using my own driver I should look into configuration space to be able to see how to communicate with AXI-Lite and how to communicate with AXI DMA because they will have to be accessed in different ways, am I wrong? Also, I would appreciate if you know some document provided by Xilinx where it is explained how to read the configuration space header, if there is no document I will try to look using another sources.

 

 

Regards,

 

Joel

 

LteDriver.JPG
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Moderator
Moderator
1,080 Views
Registered: ‎02-16-2010

Re: [BAR] Access

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In case of using Xilinx drivers I don't have to know the address, am I wrong?

Ans: You are not wrong

 

In case of using my own driver I should look into configuration space to be able to see how to communicate with AXI-Lite and how to communicate with AXI DMA because they will have to be accessed in different ways, am I wrong? 

Ans: You are not wrong

 

To read configuration space, you will need to use Type 0 Configuration Read Request

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Don't forget to reply, give kudo and accept as solution
------------------------------------------------------------------------------