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Observer
Observer
7,064 Views
Registered: ‎02-28-2009

BMD project support interrupt ?

Hello:

     I have been doing DMA work of Pcie with XIlinx BMD project Demo. For interrupt, i have duzzle for it. Can anyone help me ?

 

 

 

1、 Does BMD project Demo  suported leagcy interrupt?

 

   The logic of cfg_interrupt_rdy_n and cfg_interrupt_n in BMD_INTR_CTRL.v of BMD project  is  conflicting with  file describled in UG341.pdf.  Can anyone tell me which is correct ?

 

Actually, in Hardware test, I can get cfg_interrupt_rdy_n and cfg_interrupt_n signal time-relation with Chipscope. Please see picture(1) !

 

But I can not get this leagcy interrupt in my  Deiver tool (Windriver), meantime, the PCI STATUS register bit[3] is '0' at all times. So Is this leagcy interrupt really  transmitted by FPGA ?

 

 

 

2、 Does BMD project Demo  suported MSI interrupt?

 

  If supported, so MSI should transmitt  interrupt with Memory write request!   But in BMD project, MSI MWR logic is not existent. Is this correct?

 

 

THANKS!

 

 

Message Edited by pzczly on 10-28-2009 05:59 PM
leagcy_interrupt.JPG
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Observer
Observer
7,055 Views
Registered: ‎02-28-2009

Hello:

 

  In UG431.pdf,  file states that cfg_status[3] does not reflect the state of peding interrupt in the device/function !    But,  PCI specification  states cfg_status[3] is used to indicate

 

pending interrupt !   So, is this why ?

 

 

If I agree with UG341.pdf,  then now  How I jude leagcy interrupt in WinDriver ?   Because I can not jude interrupt through this cfg_status[3] register !

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Visitor
Visitor
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Registered: ‎10-31-2009

There is some disappointing info in this thread: 

 

http://forums.xilinx.com/xlnx/board/message?board.id=PCIe&thread.id=295

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Observer
Observer
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Registered: ‎02-28-2009

Thank you for Nreasoner!

 

 

Now, i'm duzzled!     Can anyone tell me if  BMD_project(based on xapp1052) support interrupt?

 

 

if supported, then  I send cfg_interrupt_n, cfg_interrupt_rdy_n,cfg_interrupt_assert_n which based on ug341.pdf.   Can PC system get INTA#  through configuration status register[3] ?

 

 

 

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Contributor
Contributor
6,435 Views
Registered: ‎02-18-2008

With legacy interrupts enabled, the pcie core has to first send an interrupt with "cfg_interrupt_assert_n" asserted, and then send another interrupt with "cfg_interrupt_assert_n" de-asserted.

 

We found that the core wasn't sending a de-assert interrupt, because the driver has to initiate this by setting the LEGACYCLR bit in BMD Register # 18 :

 

            // 48-4BH : Reg # 18
            // INTDI (RW)
            // INTDO
            // MMEN
            // MSIEN

            7'b010010: begin
               if (wr_en_i) begin
                  INTDI[7:0] <= wr_d_i[7:0];  
                  LEGACYCLR <= wr_d_i[8];
               end


               rd_d_o <= {4'h0,
                          cfg_interrupt_msienable,
                          cfg_interrupt_mmenable[2:0],
                          cfg_interrupt_do[7:0],
                          7'h0,
                          LEGACYCLR,
                          INTDI[7:0]};
            end

 

 

The interrupts worked once the driver was modified to do this.