Showing results for 
Search instead for 
Did you mean: 
Registered: ‎07-02-2018

Board pin assignment

I’ve created an UltraSCALE+ project for a ZCU111 board and enabled PCIe in the PS as an endpoint and want to connect the TX, RX, and REFCLK pairs from the PCIe to the SFP connector.

After synthesis the IO report indicated that the TX, RX, and REFCLK pairs got assigned to pins on the ZCU111 board that have nothing connected to it according to the schematics. The only visible IO assignments are from logic I placed into the PL design (Leds and Dip switches), and the ones belonging to other features enabled in the PS all assigned to actual hardware as checked on the schematics of the ZCU111 except for the PCIe endpoint. I made sure the board files were installed properly but no luck.

Some questions:

  1. Where in the project can I find the .XDC file or whatever file that assigns the PS assigned features to the IO pins so I can see what was assigned and perhaps edit this file – carefully.
  2. I suspect synthesis picked free unassigned pins during synthesis because perhaps the board files did not define what to do with these connections when enabling the PCIe. The connections to the SFP cage are already connected and It’s unclear which IP in the PS uses them.
  3. So, is it possible to configure the PS PCIe as an endpoint and connect it to the SFP? Or does a user not have any control of which IO pins the PS resources connect to other than having options that drop-down boxes let you choose? I would certainly understand removing the option in the case of DDR memory or RFSoC ADCs and DACs.

Thanks everyone.

0 Kudos
1 Reply
Registered: ‎02-16-2010

Re: Board pin assignment

Hi @menoch2 

Have you checked the board schematics (or) Board user guide to know if PS-GTR pins are connected to SFP?

PS pins location are fixed so the design does not need to set any IO location constraints.

Don't forget to reply, give kudo and accept as solution