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brent.aandd
Observer
Observer
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Registered: ‎02-15-2018

Bypass PCIe receiver detect on Untrascale and Ultrascale+ devices

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I know it is possible to bypass PCIe receiver detect on PCIe according to AR45859. Is this still possible with Ultrascale and Ultrascale+ devices? It is also unclear to me if Tandem reconfiguration will work well with this bypass solution. Does anybody have specific experiance to say that this will work?

Thanks!

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kurihara
Xilinx Employee
Xilinx Employee
923 Views
Registered: ‎07-26-2012

The idea is the same for Ultarascale/Ultarascale+. Refer to the Transceiver User's Guide to give a pseudo signal to the PCIe block as if a Receiver is detected and bypass it. I have not tested with Tandem, but it goes to the link up state in the 1st stage, so it seems to be the same.

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kurihara
Xilinx Employee
Xilinx Employee
924 Views
Registered: ‎07-26-2012

The idea is the same for Ultarascale/Ultarascale+. Refer to the Transceiver User's Guide to give a pseudo signal to the PCIe block as if a Receiver is detected and bypass it. I have not tested with Tandem, but it goes to the link up state in the 1st stage, so it seems to be the same.

View solution in original post

ziyi_zhu
Observer
Observer
789 Views
Registered: ‎10-15-2018

Dear Kurihara

It seems that even though I changed the wapper file for an ultrascale+ device (ZCU106, xdma IP), Vivado does not automatically resynthesize the design and it uses the old synthesized results. Am I wrong or is there a way to force Vivado to resynthesize and reimplement the modified design?

 

Thank you.

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kurihara
Xilinx Employee
Xilinx Employee
768 Views
Registered: ‎07-26-2012

When you generate IP, select "Global" instead of "Out of context per IP". Then, edit the wrapper and run synthesis. Both user design and IP wrappers will be synthesized which should have your modification in the netlist.