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min16
Observer
Observer
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Registered: ‎01-09-2018

Bypass configuration messages at endpoint (PCIE40E4)

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Hi, is there anyway to bypass configuration messages from the host to Ultrascale+ endpoint IP?

I need to build all pcie configuration spaces inside my user logic but I don't know how to let configuration messages from the host to be delivered through PCIE40E4 (PG213) IP from Xilinx.

Thank you in advance.

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min16
Observer
Observer
311 Views
Registered: ‎01-09-2018

Through some experiments, I actually found cfg_ext_* interface is outputing enough information for me even if the host is accessing configuration space not withtin 0x480-0x4ff. I'm just using this port for my purpose.

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min16
Observer
Observer
312 Views
Registered: ‎01-09-2018

Through some experiments, I actually found cfg_ext_* interface is outputing enough information for me even if the host is accessing configuration space not withtin 0x480-0x4ff. I'm just using this port for my purpose.

View solution in original post

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