05-14-2018 02:02 AM
Hello I'm working vivado 2017.4 and artix 7. I'm using DMA/Bridge Subsystem for PCI Express v4.1 to do DMA transfert C2H in a video application. I acquire a video line writing it in a block ram and during the hblank I do a single DMA transfert for each line to transfert the content of BRAM to the host specifying source, destination and length. Control is costant to 16'h3 value. In this way all works right. In the final version of my project I would need to have 3 asyncronous video sources and to transfert Y, U, V separately
so I could have in the worst case 9 DMA transfert during Hblank. The problem now is that it seems that if I do more than a DMA transfert at the end of line after a random number of transfert (that i can read in DMA interface registers) the DMA stalls. Trying to solve the problem I also enabled the dma_status_ports DMA/Bridge Subsystem for PCI Express and I'm using c2h_sts_1 (a strobe that indicate that the descriptor has been completed). I wait that c2h_sts_1 goes High and than I load the new descriptor. But also doing this nothing change. What could be the mistake? Thank you.
05-18-2018 01:26 AM - edited 05-18-2018 01:28 AM
I solved the problem with a workaround. DMA start, fpga wait for the ack c2h_sts_1 on dma status port signaling that the descriptor has been executed. The ack reset a timer and after minimum 16 clock cycles I do next DMA transfert. It works to solve my problem but I would want to understand because without this workaround DMA stall also because this workaround is very sub-optimal reguarding descriptor bypass throughput . Thank you.