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Participant darin_i
Participant
811 Views
Registered: ‎02-15-2018

C2H destination alignment

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Colleagues,

 

I'm working on a (my first) PCIe card design for a multi-stream data acquisition system. I need to bring in 16-bit data from data sources and DMA it into GPU memory. I'll be using one C2H channel per stream. I'm using Kintex-7 parts and the PCIe 2.0 hard block.

 

What I'd like to do is have the DMA operation end up planting the data in the GPU's memory with 32-bit address increments to align it for downstream processing (otherwise the software folks have to instantiate another kernel in the GPU to do this). So in other words, because PCIe operations are a transaction 'packet' I'd like to have the destination take the first 16 bits and sick them at address offset 0x0000 in the GPU, the second at 0x0004, etc.

 

I've read through ug195 and some other online resource, but it seems I may be WTFOB with wanting this.

 

Any suggestions would be appreciated.

 

Thanks!

 

 

 

 

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Participant darin_i
Participant
718 Views
Registered: ‎02-15-2018

Re: C2H destination alignment

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Actually, I think I found the solution...

 

I'm trying to bring in six 16-bit ADC inputs all clocked from a common sample clock. I want to stream these via C2H dma channel to a PCIe host. It looks like a FIFO and an AXI stream data width converter does what I want. I can see the words get clocked in 96-bits wide at the sample rate and see 128-bit data get stuffed into the C2H stream input of the xdma IP.

 

Thanks

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2 Replies
Xilinx Employee
Xilinx Employee
729 Views
Registered: ‎12-10-2013

Re: C2H destination alignment

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I'm a little lost on what you are trying to do.  Could you diagram this out, or give an example?   Are you wanting every 16 bits zero padded with an addition 16bits?

 

Thanks!

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Participant darin_i
Participant
719 Views
Registered: ‎02-15-2018

Re: C2H destination alignment

Jump to solution

Actually, I think I found the solution...

 

I'm trying to bring in six 16-bit ADC inputs all clocked from a common sample clock. I want to stream these via C2H dma channel to a PCIe host. It looks like a FIFO and an AXI stream data width converter does what I want. I can see the words get clocked in 96-bits wide at the sample rate and see 128-bit data get stuffed into the C2H stream input of the xdma IP.

 

Thanks

View solution in original post

0 Kudos