03-30-2020 01:05 AM
I am using Artix-7 FPGAs XC7A200T FBG676pin.
Using PCIe-Gen 2 with Hard-IP in a 1 Lane configuration.
Is it possible to realize another PCIe Lane with soft macro?
04-02-2020 02:39 AM
hello @debudebutti ,
yes you can implement using the GTP transceiver , which offers a data rate range and features that allow physical layer support for various protocols including: • PCI Express, Revision 1.1/2.0 .
04-02-2020 02:39 AM
hello @debudebutti ,
yes you can implement using the GTP transceiver , which offers a data rate range and features that allow physical layer support for various protocols including: • PCI Express, Revision 1.1/2.0 .
04-06-2020 10:17 PM
Thank you for an answer.
I understood the solution.