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Contributor
Contributor
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Registered: ‎12-02-2014

Can a PCIe endpoint have several outbound request with same TAG?

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I aware that if an PCIe Endpoint send several read request to the host, the completion packets returned may not be in order, and then we need the TAG field to reorder them.

But I want to know if there is another way to identify the cpld TLP?

For example, if I send 2 read request of 128 Bytes with the same TAG to the host, by return, if the CPLDs don't arrive in order, then is there any chance that I can identify and reorder them?

 

 

 

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Adventurer
Adventurer
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Registered: ‎08-07-2014

For example, if I send 2 read request of 128 Bytes with the same TAG to the host, by return, if the CPLDs don't arrive in order, then is there any chance that I can identify and reorder them?

 


Well... my understanding is that you shouldn't. My reference is the PG023:

 

"External Tag Management: This mode of operation is selected by setting the

AXISTEN_IF_ENABLE_user_TAG parameter to 1. In this mode, the user logic is
responsible for allocating the tag for each Non-Posted request initiated from the
requester side. The user logic must choose the tag value without conflicting with the
tags of all other Non-Posted transactions outstanding at that time, and must
communicate this chosen tag value to integrated block through the request descriptor."

 

There's another explanation in this document telling that TAGs can just be reused upon completion. In other words,  is that you can't (or shouldn't) send 2 "on-the-fly" (outstanding) read request with the same TAG. You should receive the completion to send the second request, or choose another tag.

 

regards

Lucas

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Xilinx Employee
Xilinx Employee
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Registered: ‎11-25-2015

Hi Collipisc,

 

As per my understanding, individual tag mechanism for each memory read request in PCIe protocol is recommended(reduction in round trip delay and latency in reads)

 

I am not sure if it's an Error scenario as per PCIe protocol because it expects different tag for the next coming memory read requests

 

Note: In general, Xilinx PCIe IP's doesn't have support for getting the out of order completions to come in order for multiple read requests

 

Thanks,

Sethu

 

 

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Adventurer
Adventurer
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Registered: ‎08-07-2014

For example, if I send 2 read request of 128 Bytes with the same TAG to the host, by return, if the CPLDs don't arrive in order, then is there any chance that I can identify and reorder them?

 


Well... my understanding is that you shouldn't. My reference is the PG023:

 

"External Tag Management: This mode of operation is selected by setting the

AXISTEN_IF_ENABLE_user_TAG parameter to 1. In this mode, the user logic is
responsible for allocating the tag for each Non-Posted request initiated from the
requester side. The user logic must choose the tag value without conflicting with the
tags of all other Non-Posted transactions outstanding at that time, and must
communicate this chosen tag value to integrated block through the request descriptor."

 

There's another explanation in this document telling that TAGs can just be reused upon completion. In other words,  is that you can't (or shouldn't) send 2 "on-the-fly" (outstanding) read request with the same TAG. You should receive the completion to send the second request, or choose another tag.

 

regards

Lucas

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