09-07-2020 07:30 PM
We tried to communicate to a ddr4 sdram through the pcie to axi channel, we used qdma ip with one BAR configured to axi bridge master, but since the ddr4 is 16GB, and the pcie bar space can not be too large(maybe only 128M or 256M), so is there any way to configure the address of pcie to axi translation dynamically, by this way, we can read and write the ddr4 spaces in segments.
11-02-2020 06:53 AM
in the following Xilinx page:
you can find a series of tactical patches for the QDMA IP version 3.0 and 4.0.
Don't know if this could be helpful.
01-14-2021 07:26 AM
Hi @dlfc ,
a possible solution could be the usage of PCIe "Resizable BAR" capability.
As reported in PCI-SIG 3.0 documentation (sec. 7.22 - Resizable BAR Capability):
"The Resizable BAR Capability is an optional capability that allows hardware to communicate
resource sizes, and system software, after determining the optimal size, to communicate this optimal
size back to the hardware. Hardware communicates the resource sizes that are acceptable for
operation via the Resizable BAR Capability register. Software determines, through a proprietary
mechanism, what the optimal size is for the resource, and programs that size via the BAR Size field
of the Resizable BAR Control register. Hardware immediately reflects the size inference in the read-
only bits of the appropriate Base Address register. Hardware must Clear any bits that change from
RW to read-only, so that subsequent reads return zero. Software must clear the Memory Space
Enable bit in the Command register before writing the BAR Size field. After writing the BAR Size
field, the contents of the corresponding BAR are undefined. To ensure that it contains a valid
address after resizing the BAR, system software must reprogram the BAR, and Set the Memory
Space Enable bit (unless the resource is not allocated).
The Resizable BAR Capability register is permitted to indicate the ability to operate at 4 GB or
greater only if the associated BAR is a 64-bit BAR.
This capability is applicable to Functions that have Base Address registers only. It is strongly
recommended that a Function not advertise any supported BAR sizes in its Resizable BAR
Capability register that are larger than the space it would effectively utilize if allocated."
I don't know if this capability is supported by Xilinx PCIe IP.