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dlfc
Adventurer
Adventurer
770 Views
Registered: ‎05-04-2017

Can the address of pcie to axi translation to be configured dynamically?

We tried to communicate to a ddr4 sdram through the pcie to axi channel, we used qdma ip with one BAR configured to axi bridge master, but since the ddr4 is 16GB, and the pcie bar space can not be too large(maybe only 128M or 256M), so is there any way to configure the address of pcie to axi translation dynamically, by this way, we can read and write the ddr4 spaces in segments.

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5 Replies
mmcnicho
Xilinx Employee
Xilinx Employee
664 Views
Registered: ‎10-09-2019

Hi,

I wanted to check if you have tried setting the PCIe BAR size to 16GB?

Thanks,

Matt

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dlfc
Adventurer
Adventurer
651 Views
Registered: ‎05-04-2017

I had tried,  the server can't get up when the pcie bar space is over 4 gigabytes, bios is failed to load in.

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mshin
Contributor
Contributor
533 Views
Registered: ‎02-14-2014

Same issue when using Axi Memory Mapped PCIe and setting the translation more than 512MB. 

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dsakjl
Explorer
Explorer
479 Views
Registered: ‎07-20-2018

Hello everyone,

in the following Xilinx page:

https://www.xilinx.com/support/answers/70927.html

you can find a series of tactical patches for the QDMA IP version 3.0 and 4.0.

Don't know if this could be helpful.

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dsakjl
Explorer
Explorer
263 Views
Registered: ‎07-20-2018

Hi @dlfc ,

a possible solution could be the usage of PCIe "Resizable BAR" capability.

As reported in PCI-SIG 3.0 documentation (sec. 7.22 - Resizable BAR Capability):

"The Resizable BAR Capability is an optional capability that allows hardware to communicate
resource sizes, and system software, after determining the optimal size, to communicate this optimal
size back to the hardware. Hardware communicates the resource sizes that are acceptable for
operation via the Resizable BAR Capability register. Software determines, through a proprietary
mechanism, what the optimal size is for the resource, and programs that size via the BAR Size field
of the Resizable BAR Control register. Hardware immediately reflects the size inference in the read-
only bits of the appropriate Base Address register. Hardware must Clear any bits that change from
RW to read-only, so that subsequent reads return zero. Software must clear the Memory Space
Enable bit in the Command register before writing the BAR Size field. After writing the BAR Size
field, the contents of the corresponding BAR are undefined. To ensure that it contains a valid
address after resizing the BAR, system software must reprogram the BAR, and Set the Memory
Space Enable bit (unless the resource is not allocated).
The Resizable BAR Capability register is permitted to indicate the ability to operate at 4 GB or
greater only if the associated BAR is a 64-bit BAR.
This capability is applicable to Functions that have Base Address registers only. It is strongly
recommended that a Function not advertise any supported BAR sizes in its Resizable BAR
Capability register that are larger than the space it would effectively utilize if allocated."

I don't know if this capability is supported by Xilinx PCIe IP.

Regards.

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