UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

cancel
Showing results for 
Search instead for 
Did you mean: 
232 Views
Registered: ‎04-01-2019

Can we control (reduce/increase) link speed & link width from EP side without modifying anything at root port?

Can we reduce or increase link width/link speed from EP side, without modifyign anything at root port.

In simple words, can we control or adjust link speed or link width from EP?

Tags (1)
0 Kudos
2 Replies
Xilinx Employee
Xilinx Employee
189 Views
Registered: ‎08-06-2008

Re: Can we control (reduce/increase) link speed & link width from EP side without modifying anything at root port?

You could tape off the lanes as described in the link below: https://www.xilinx.com/support/answers/38988.html Thanks.
0 Kudos
185 Views
Registered: ‎04-01-2019

Re: Can we control (reduce/increase) link speed & link width from EP side without modifying anything at root port?

Yes, we can tape off the lanes using 'lane reducers', but controlling from configuration registers is required PCIe feature or not.

0 Kudos