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368 Views
Registered: ‎04-01-2019

Can we control (reduce/increase) link speed & link width from EP side without modifying anything at root port?

Can we reduce or increase link width/link speed from EP side, without modifyign anything at root port.

In simple words, can we control or adjust link speed or link width from EP?

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Xilinx Employee
Xilinx Employee
325 Views
Registered: ‎08-06-2008

You could tape off the lanes as described in the link below: https://www.xilinx.com/support/answers/38988.html Thanks.
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321 Views
Registered: ‎04-01-2019

Yes, we can tape off the lanes using 'lane reducers', but controlling from configuration registers is required PCIe feature or not.

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