01-02-2019 10:20 PM
In zynq, XAZU5EV-SFV784-Q, Is it possible to have two PCIe RC in PL section? One PCIe with block location X0Y0, x2 @gen3 and another PCIe with block location X0Y1, x2 @gen3.
When I tried to implement, Placement failed saying that it is incompatible with the device sometimes, sometimes implementation got successful. Can you please check on this and give me a clear idea on this? FYI, we have only one MGT bank in bank 224 where we have 4 MGTREFCLK pins and 8 transceiver pins. Is it really compatible?
The error is :
[Place 30-60] Place Check : This design requires more GTHE4_COMMON cells than are available in the target device. This design requires 2 of such cell types but only 1 compatible site is available in the target device. please analyze your synthesis results and constraints to ensure the design is mapped to Xilinx primitives as expected.
How to overcome this issue?
01-03-2019 08:05 AM
While there are two PCIE sites (X0Y0 & X0Y1), there is only one available GTHE4_COMMON (GTHE4_COMMON_X0Y1). There are actually 4 listed from a search, but only one is bonded/usable. I would check to see if there is a shared resources option in the IP core.
Don’t forget to reply, kudo, and accept as solution.
01-03-2019 08:14 AM - edited 01-03-2019 09:04 PM
Yeah, please check.
Can you clarify whether two PCIes of same block location is possible (as both the blocks are in same bank)? Two PCIe of same block X0Y1 will work?
01-24-2019 10:39 AM
Sorry to keep you in the dark for so long. You should be able to share 2 PCIe Blocks in a Single Quad using a Single Refclk, but there are MANY considerations to think about.
You have to share the GT_COMMON between the two PCIe Blocks. The easiest way to do this is by configuring both IP in the "Shared Logic" tab to "Include GT COMMON in Example Design."
You also need to enable clock sharing as documented in AR69405 (You must do steps 1-4). We will be using the Example Design moving forward, but this logic can be applied on your actual application, but will be more complicated.
AR69405 Steps to Clock Share:
1. In DMA Subsystem for PCI Express or PCI Express Integrated Block, set the following property in the Vivado Tcl console:
set_property CONFIG.ext_sys_clk_bufg true [get_ips <ip_name>]
set_property CONFIG.ext_sys_clk_bufg true [get_bd_cells <ip_name>]
2. Reset Output Products on the IP or your Block Design and Regenerate Output Products again to have the new settings applied to the design.
3. Instantiate BUFG_GT and BUFG_GT_SYNC in your design as follows:
4. Add/Replace the following ports in your DMA Subsystem for PCI Express or PCI Express Integrated Block IP instantiation:
You can now "Open IP Example Design" for BOTH IP.
Once you have BOTH example design's up you will see a hiearchy that looks like the following in each Eaxmple. We pull the GT_COMMON outside of the IP and put it in the Support Wrapper.
You will then have to splice together the two example designs making sure to remove the GT_COMMON from ONE of the IP Example Designs and then connect the SHARED GT_COMMON between the two. It should look something like the following:
Which would look like this in Project Hierarchy:
As you can see Example Design 1 has unique filenames and module names. You need to make sure and make these changes to Example Design 1 (BEFORE) importing it into Example Design 0.
You will also need to take care of constraints in both Example Designs as the PATH's probably change when you combined the projects and you may also need to add unique naming to BUFG's and stuff like that.
You need to go into the Example Design 1 *_gt.xdc and change the GT_CHANNEL lanes to alternate locations in the quad.
Once you have done ALL these modifications you should be able to implement without any DRC's or errors.
01-28-2019 05:02 AM - edited 01-28-2019 05:09 AM
Thank you so much for your support. It really helped me to have two PCIe RC in One zynq device. But im facing issue while validating design and address editor. First of all, i'm perplexed to have two master and two slave or one master and one slave in ZYNQ ultrascale PS section. Eventhough i tried with two designs but validating is failed due to following errors(attached) and unmapped slaves.
Eventhough all interfaces are connected properly, why 'unmapped slaves' occurs in address editor?
Please help me which will be the optimized design that will fit according to my requirement?
01-28-2019 03:25 PM
There is something not quite right with your IPI blocks. There are many missing ports from your SmartConnects and XDMA IP. Are these custom IP?
01-29-2019 03:08 AM
Zynq PS and XDMA are customized (One at X0Y0 and another at X0Y1), as shown in the figure. Then 'Run connection automation' and 'Run Block automation' was run. Same procedure was followed with one PCIe at PL section of Zynq, It was working fine. But for two PCIe, I'm facing these mentioned issues. Can you please guide me how to design proper IPI block for this interface? As I dont know where this is going wrong, It will be very much helpful to rectify this.