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abitofmaya
Adventurer
Adventurer
438 Views
Registered: ‎08-27-2018

Cannot generate example design for Versal ACAP Integrated Block for PCI Express on Vivado 2021.1.

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I am trying to generate the example design for Versal ACAP Integrated Block for PCI Express on Vivado 2021.1 for Versal AI Core Series VCK190. I am getting the following error. I did check the location of the files. The SRIOV_EXD folder does not exist.

Is this an issue with the 2020.1 release? I did generate the design on Vivado 2020.3 and it worked fine. I upgraded the same example which also did not work.

 

INFO: [IP_Flow 19-1686] Generating 'Examples' target for IP 'pcie_versal_0'...
ERROR: [IP_Flow 19-682] TTCL input file 'e:/Xilinx/Vivado/2021.1/data/ip/xilinx/pcie_versal_v1_0/ttcl/SRIOV_EXD/sriov_tx_engine_v.ttcl' is not readable.
ERROR: [IP_Flow 19-677] Failed to convert TTCL input file 'e:/Xilinx/Vivado/2021.1/data/ip/xilinx/pcie_versal_v1_0/ttcl/SRIOV_EXD/sriov_tx_engine_v.ttcl'.
CRITICAL WARNING: [IP_Flow 19-1747] Failed to deliver file 'e:/Xilinx/Vivado/2021.1/data/ip/xilinx/pcie_versal_v1_0/ttcl/SRIOV_EXD/sriov_tx_engine_v.ttcl': Problem reading TTCL file
ERROR: [IP_Flow 19-167] Failed to deliver one or more file(s).
ERROR: [IP_Flow 19-3505] IP Generation error: Failed to generate IP 'pcie_versal_0'. Failed to generate 'Any Language Examples' outputs:
ERROR: [IP_Flow 19-98] Generation of the IP CORE failed.
Failed to generate IP 'pcie_versal_0'. Failed to generate 'Any Language Examples' outputs:
INFO: [Common 17-206] Exiting Vivado at Fri Jul 16 15:42:37 2021...

 

 

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abitofmaya
Adventurer
Adventurer
260 Views
Registered: ‎08-27-2018

Hi, @pvenugo, @garethc,

It was an installation problem, I think. I reinstalled Vitis and it worked. Thank You.

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3 Replies
garethc
Moderator
Moderator
303 Views
Registered: ‎06-29-2011

Hi @abitofmaya 

Can you send me the XCI file for the PCIe IP you are using and I will investigate this and get back to you.

Thanks,

Gareth


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pvenugo
Moderator
Moderator
295 Views
Registered: ‎07-31-2012

Hi @abitofmaya ,

I've tried to generate Versal Integrated PCIe example design in 2021.1 and was successful.

Could you share the xci file?

 

Regards

Praveen


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abitofmaya
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Registered: ‎08-27-2018

Hi, @pvenugo, @garethc,

It was an installation problem, I think. I reinstalled Vitis and it worked. Thank You.

View solution in original post