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paulwittib
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Registered: ‎06-22-2009

Changing Vendor ID in PCIe core does not seem to "take" still reading out Xilinx's Vendor ID

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I have instantiated a PCIe core in my design.  The core communicates with the PIO Example code which I have modified to access a bunch of register space (my application code.)  I compile this design and it appears to work fine, I can read and write my register space as desired.  I am using ISE 13.1 on a Windows7 box.  Using SP605 eval board.   The PCIe core is instantiated as a bunch of VHDL with the axi_basic_top all verilog. 

 

I reconfigured the PCIe core via CoreGen to implement our Vendor ID, Device ID, etc.  These values are not changing for me.  I notice that they are changing in PCIe.vhd (see below.)  When I read the SP605 eval board with my utility (RW Everything) I still get the Xilinx Vendor ID and Device ID.  Moreover I am trying to update my BAR space and these changes are not "taking" either.

 

    CFG_VEN_ID                        : std_logic_vector(15 downto 0) := x"1187";
    CFG_DEV_ID                        : std_logic_vector(15 downto 0) := x"0001";
    CFG_REV_ID                        : std_logic_vector(7 downto 0)  := x"01";
    CFG_SUBSYS_VEN_ID                 : std_logic_vector(15 downto 0) := x"1187";
    CFG_SUBSYS_ID                     : std_logic_vector(15 downto 0) := x"0001";
    REF_CLK_FREQ                      : integer    := 1
  );

 

I have tried several things like cleaning project files (then recompiling my code, downloading, reading PCIe devices using my utility.)  I know my recompile-download process is working because I change a canned register value that I can read out using my utility, it changes everytime as expected.  I have also tried reconfiguring the core a few times and re-saving the PCIe VHDL files so ISE recognizes them as "changed."

 

What am I doing wrong?  Why can't I change the Vendor ID?  Any ideas would be much appreciated. 

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paulwittib
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Registered: ‎06-22-2009

Found my problem.  I wasn't updating the generic assignments on the next level up from PCIe.vhd, they were getting overriden by my version of xilinx_pcie_1_1_ep_s6.vhd.  Oops.

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luisb
Xilinx Employee
Xilinx Employee
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Registered: ‎04-06-2010

I would double check that you're compiling the correct files.  You should be able to look at your synthesis report to see what files are being synthesize.  Sometime, synthesizers create a directory were compiled files are kept and if the file doesn't change it does not re-compile the file.  You may want to delete this folder.  

 

The core simply take the CFG_VEN_ID generatic and assigns it to a signal called w_cfg_ven_id.  This signal is then assigned to the port on the PCIe hardblock called, "CFGVENID".  This should be pretty straight forward.  If you want, you can check that they are assigned correct in PlanAhead by looking at the CFGVENID pin of the PCIe hardblock.

 

Can you also let us know what synthesizer you're using?  I want to make sure that you're synthesizing with XST.

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paulwittib
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Registered: ‎06-22-2009

Using XST for synthesizer. 

I started another project from scratch along with a new PCIe core with the settings I want.  This worked.  So you're right, it must be some file that is not getting cleaned when I "clean" the project.  Anyway...I will investigate your suggestion.  Either way I think I can handle it from here.  Thanks

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paulwittib
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Registered: ‎06-22-2009

Found my problem.  I wasn't updating the generic assignments on the next level up from PCIe.vhd, they were getting overriden by my version of xilinx_pcie_1_1_ep_s6.vhd.  Oops.

View solution in original post

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