06-13-2018 12:40 AM
I want to implement a "32-bit Initiator/Target for PCI (7-Series)" IP-Core (Yes, the old stuff. For us it is still alive and kicking) into an Artix-7 XC7A15TFTG256. I'm using Vivado 2017.3.
I had to open the example design to get a constraints file for the core. This .xdc places the complete PCI interface into the bank 14, leaving no unoccupied pins in this bank. But bank 14 is also used for configuration, resulting in a bunch of conflicting pins.
Besides that, the pinout is fubar in a way that makes it very hard to layout the PCI interface on a PCB, if even possible.
UG262 tells me to "not modify the provided constraint’s file pin placement". Together this is making an implementation practical impossible.
1. Is the restriction to "not modify the provided constraint’s file pin placement" still valid (it is from 2012...)? Or can I change pin locations when necessary?
2. Can I somehow get a constraints file that has pin locations that are possible to implement?
07-02-2018 12:32 AM
06-25-2018 09:43 AM
May be I misunderstood. In the tool, I see the config pins are in Bank-0 in the device you referred.
Could you please confirm?
06-25-2018 11:55 PM - edited 06-26-2018 03:14 AM
I made a up a testcase, see the attached files. Place both files in a folder. Rename "pci_test.xdc.txt" to "pci_test.xdc" (It won't let me upload a .xdc file...). Source the "recreate_project.tcl".
The "pci_text.xdc" does nothing more than to prohibit the pins necessary for the SPI configuration interface, and to set a "CLOCK_DEDICATED_ROUTE FALSE" constraint (see the change notes in AR# 70699).
The "recreate_project.tcl" creates a project, creates the PCI ip and the example design, and adds the example designs files and the "pci_text.xdc" to the project. Finally it starts an implementation run, which will fail with messages like:
[Place 30-25] Component XPCI_WRAP/XPCI_IDSEL has been locked to a prohibited site K16.
While you're at it, also take a look at the bunch of critical warnings. These are thrown because the core's constraints files gets the hierarchy wrong: XPCI_WRAP/XPCI_CORE/inst/xst_pci/pci32_inst must be XPCI_WRAP/XPCI_CORE/U0/xst_pci/pci32_inst It should be easy to fix that.
Edit: The wrong hierarchy has already been fixed in Vivado 2018.1. \o/
06-26-2018 01:47 AM
to set a "CLOCK_DEDICATED_ROUTE FALSE" constraint (see the change notes in AR# 70699).
Just a remark to this constraint: There is a BUFG inserted for RST_N. This is in compliance with UG472 ("The clock trees can also be used to drive logic resources such as reset or clock enable"), but seems to make the "CLOCK_DEDICATED_ROUTE FALSE" necessary for RST_N. This can be avoided when RST_N is located on a clock capable pin.
07-02-2018 12:32 AM