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Observer
Observer
9,011 Views
Registered: ‎12-28-2013

Confusing Completion Timeout

Hi everyone,

        I'm now using the V7 PCIe Gen3 endpoint core in my project which involves data tranmission from FPGA to x86 by

dma.The simulation works well, and cpu receives all the data correctly in hardware debug.  What confuses me is that  in hardware debug, FPGA receives a tlp with an error coded 1001, indicating  "Request terminated by a Completion timeout".  But the completion timeout mechanism will only start after receiving a read request. 

       How to accout for this? I need your help.

       Thank you!

 

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Scholar
Scholar
8,991 Views
Registered: ‎02-03-2010

Re: Confusing Completion Timeout

Hi,

 

Can you check "Request Completed bit" set while sening the final completion packets of all out standing requests ?

Are there any errors indicated by link partner at this time ?

 

Regards,

Koti Reddy

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