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skr1
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Registered: ‎01-04-2021

Connecting PCIe endpoint with root complex using xilinx example aplications

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Hi! I'm using Vivado 2019.2, 7 Series Integrated Block for PCI Express, and two XC7A75TFGG. 

I'm trying to connect the chips with PCIe, programming one as RC and second as EP, using the example applications. 

The link up is asserted and link training is established successfully. But when the data is sent from the RC to the EP, the EP doesn't return the expected data.

I found this: https://forums.xilinx.com/t5/PCIe-and-CPM/Problems-connecting-EP-and-RC/m-p/289725#M4148

So I know that examples won't work together by default. But I don't know how to change the mentioned addresses. I assume this is about BARs? Could someone help me determine what I need to change in the examples to make this work?

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skr1
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Registered: ‎01-04-2021

Ok, I've figured it out. The EP BAR value must not be the same as the RP BAR value. I've used values from the simulation, that's bar_0=FFE0000C for EP and bar_0=FFFFF804 for RC (if you use a single 32 bit BAR).

You cannot change these values in PCIe IP configurator (BARs tab) for some reason so you have to modify core files. Is that a Vivado bug?

 

EDIT: The bar value is just a representation of the BAR settings, it's not an address or an offset. For End Point, the BAR settings need to follow certain limitations for it to work. From the datasheet:

"When configuring the core as an Endpoint for PCIe (non-Legacy), 64-bit addressing must be supported for all BARs (except BAR5) that have the prefetchable bit set. 32-bit addressing is permitted for all BARs that do not have the prefetchable bit set. The prefetchable bit related requirement does not apply to a Legacy Endpoint. The minimum memory address range supported by a BAR is 128 bytes for a PCI Express Endpoint and 16 bytes for a Legacy PCI Express Endpoint."

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skr1
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Registered: ‎01-04-2021

Ok, I've figured it out. The EP BAR value must not be the same as the RP BAR value. I've used values from the simulation, that's bar_0=FFE0000C for EP and bar_0=FFFFF804 for RC (if you use a single 32 bit BAR).

You cannot change these values in PCIe IP configurator (BARs tab) for some reason so you have to modify core files. Is that a Vivado bug?

 

EDIT: The bar value is just a representation of the BAR settings, it's not an address or an offset. For End Point, the BAR settings need to follow certain limitations for it to work. From the datasheet:

"When configuring the core as an Endpoint for PCIe (non-Legacy), 64-bit addressing must be supported for all BARs (except BAR5) that have the prefetchable bit set. 32-bit addressing is permitted for all BARs that do not have the prefetchable bit set. The prefetchable bit related requirement does not apply to a Legacy Endpoint. The minimum memory address range supported by a BAR is 128 bytes for a PCI Express Endpoint and 16 bytes for a Legacy PCI Express Endpoint."

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