DMA/Bridge Subsystem for PCI Express AXI Bridge Advanced Mode: AWReady/WReady Never Assertes

[jfrye_wmi]

Hello I am trying to perform a memory transfer with an AXI master writing to host memory from an FPGA connected to a host machine over PCI. Everything seems to be set up properly; the endpoint enumerates during host reboot and the host can write to the FPGA AXI address space using sysfs-pci. However, it does not appear that the FPGA can write to the host's memory. For whatever reason, it appears that AWReady and WReady signals are never asserted from the S_AXI_B slave interface on the DMA/Bridge Subsystem. Note that the DMA/Bridge Subsystem AXIBAR2PCIEBAR_0L register (0x203) offset has been programmed with a physical address in the host and the host software keeps a corresponding virtual address to access this data to check it. The data never appears to be sent over the PCI link to the host.

Does anyone have any thoughts as to why this might be?

[deepeshm]

Please check if Bus Master Enable bit in the Command Register is set or not.

Thanks.

[jfrye_wmi]

@deepeshm 

What's the offset? Can't find it in these documents.

https://www.xilinx.com/support/documentation/ip_documentation/axi_pcie3/v3_0/pg194-axi-bridge-pcie-gen3.pdf

https://www.xilinx.com/support/documentation/ip_documentation/xdma/v4_1/pg195-pcie-dma.pdf

[deepeshm]

Please check page-83 in the document below:

https://www.xilinx.com/support/documentation/ip_documentation/pcie4_uscale_plus/v1_3/pg213-pcie4-ultrascale-plus.pdf

The offset address is 04.

[jfrye_wmi]

Command register is 0003.

I looked at https://wiki.osdev.org/PCI#Configuration_Space

If this is right, then Memory Space and I/O Space are set and Bus Master is not.

How can I enable this? I tried writing 0007 to this register and it did not appear to take the value.

UPDATE: I enabled it with 

$: setpci -s 02:00.0 COMMAND.w=0007

Is there a way to enable this in the config space by default in the core gen?

[deepeshm]

This can't be pre-programmed. Please check the following signal. This is from PG213.

Another test you could do is, implement the base IP i.e. the IP in PG213, program the command register as you did and read it back. See if you get the correct value back.

[Jerry_sniper]

As you mentioned we needed to write comand register to 0x7. Now I already wrote comand register to 0x7 from root pointer through config packet. And configure reading operation is also show the value is "0010_0007". But the end_port port cfg_mgmt_function_status is still show 0003. Why? If you said I must wait the  cfg_mgmt_function_status is still show 0007. How to get this point?

[Jerry_sniper]

The below figure is simulation waveform

[Jerry_sniper]

The above figure is show error signal, the right figure is as below

[Jerry_sniper]

Who know the reason why RP writing/reading command register value is different with EP port cfg_function_status at simulation? Thanks very much!