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Visitor
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Registered: ‎01-30-2019

DMA/Bridge Subsystem for PCI Express v4.0 multiple MSI-X generation

I am in the intitial planning stages for a PCIE/AXI subsystem in an ultrascale+ architecture using MSI-X interrupts.  I am using the

Xilinx DMA/Bridge Subsystem for PCI Express in AXI Bridge mode for UltraScale+™ devices.

After studying PG194, it appears that this Subsystem only allows 16 user generated MSI-X interrupts.  These interrupts are then each assigned a VECTOR_NUMBER via the "IRQ Block User Vector Number Register."  This vector number assigned to a MESSAGE DATA and a MESSAGE ADDRESS according to the MSI-X VECTOR TABLE. 

Correct? 

I was hoping to use more than 16 user generated MSI-X interrupts - the UltraScale+ Devices Block for PCIe v1.1guide (PG213) indicates that it can support the full 2048 MSI-X Interrupts from the PCIE spec.  Does the BRIDGE cause us to truly be limited to 16? 

 

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Moderator
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Registered: ‎02-16-2010

After studying PG194, it appears that this Subsystem only allows 16 user generated MSI-X interrupts.  These interrupts are then each assigned a VECTOR_NUMBER via the "IRQ Block User Vector Number Register."  This vector number assigned to a MESSAGE DATA and a MESSAGE ADDRESS according to the MSI-X VECTOR TABLE. 

Correct? 

Your understanding is correct when MSI-X interrupt implementation location is selected as "Internal".

If you use XDMA IP in "AXI Bridge" mode, you can select MSI-X interrupt implementation location is selected as "external". This allows implementing more than 16 user interrupts. However, please note that the vector table and the PBA registers need to be implemented outside the IP. 

To select MSI-X interrupt implementation location is selected as "external", you will need to change the mode in the first tab of the IP GUI to "Advanced".

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