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187 Views
Registered: ‎10-15-2019

DMA/Bridge Subsystem for PCI Express

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when i used XDMA ipcore, i met a problem about simulation that the signals of XDMA top level were always Z or X. 

my steps:

1. generate xdma ip core from IP catalog and generate a example design.

2.run simulation in example design project (board.v set as top)

but signals in the top level were Z or X 

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Xilinx Employee
Xilinx Employee
133 Views
Registered: ‎08-02-2007

回复: DMA/Bridge Subsystem for PCI Express

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Please check the log console to see if the link is up now or is there any error?

 

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Xilinx Employee
Xilinx Employee
134 Views
Registered: ‎08-02-2007

回复: DMA/Bridge Subsystem for PCI Express

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Please check the log console to see if the link is up now or is there any error?

 

------------------------------------------------------------------------------
Don't forget to reply, give kudo and accept as solution
------------------------------------------------------------------------------
106 Views
Registered: ‎10-15-2019

回复: DMA/Bridge Subsystem for PCI Express

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Thanks, i'm afraid of there are something wrongs about vivado  i donwloaded. And i changed the version of vivado into version2018, transaction link was up and the signals in simulation were present.

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