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Visitor daniel_cain
Registered: ‎11-13-2017

DMA/Bridge Subsystem for PCIe AXI Stream c2h interface

Thanks in advance for any help.


I am working on an application where a ZC706 eval board passes ADC data to a Linux computer through a Gen 2 x4 PCIe slot. I have successfully implemented the loopback example designs and the AR#65444 driver on Linux: everything works great. Now I am trying to show that we can read arbitrary data (C2H) from the FPGA using the "./dma_from_device" command.


I have removed the loopback configuration and attempted to send constant data defined in user logic, but every time I attempt to initiate a dma_from_device transfer, my Linux machine hangs and eventually crashes. I am currently not doing anything with the H2C transfer, and the project builds correctly.


I have looked at posts with similar problems, but most of them have no solutions and the ones that did haven't helped me identify my problem.


My question is: what is the correct way to allow a standalone C2H transfer over PCIe on the ZC706?


Thanks again.

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3 Replies
Registered: ‎11-09-2017

Re: DMA/Bridge Subsystem for PCIe AXI Stream c2h interface

I would like to follow-up on this inquiry and try to give it more exposure.


My setup:

NVIDIA Jetson TX2 with 4.4.38-tegra kernel

Vivado 2017.2.1

Zynq ZC706 development kit

IP Config: x4, reflck 100MHz, 5.0GT/s, 64-bit AXI width (streaming), AXI Clck 250 MHz, 1 H2C, 1 C2H, MSI-X enabled (everything else is default)


I am having the same issue with the streaming interface. I had the reference design working (so I thought) and then ripped out the H2C path and put a streaming FIFO on the C2H path. That's when I noticed the hangup, similar to Daniel. So I reverted back and reconnected the loopback path... it still hangs. Okay... so I went all the way back and went through the steps of creating a a fresh DMA/PCIe subsystem example design and it still hangs. I've tried recompiling the drivers and the user code as well. 


Basically, I can't even get the example (loopback) design to run through the standard test script (sudo ./run_test). It appears to configure the C2H channel, then hangs at the "host memory buffer = 0x414000" print statement.


I'm running through some debugging steps, following the call stack in the device driver/host app and adding some probes to ILA. But I wanted to give this inquiry more exposure because I've seen a couple other similar questions with no resolutions!


This seems like an important issue that needs resolved (beit a user error or an error with the core/driver).


I will follow-up with my debugging results.


EDIT: added my system configuration and my .xdc file (the source verilog is the default with LEDs added)

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Registered: ‎11-09-2017

Re: DMA/Bridge Subsystem for PCIe AXI Stream c2h interface

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Registered: ‎11-09-2017

Re: DMA/Bridge Subsystem for PCIe AXI Stream c2h interface

Quick update:


I was able to resolve part of my issues. That is, I was finally able to get the Xilinx example reference design to run again without hanging. The issue: MSI-X enabled (with MSI disabled?). 

The solution: Disable MSI-X and enable MSI.


Both Xilinx and the host (TX2) advertised MSI-X support, so not sure why it was failing. Nevertheless, MSI-X is not a requirement so I will not try to resolve that issue any further (hopefully someone from Xilinx will)


I will try this fix on my FIFO design tomorrow to see if it also resolves that issue.


EDIT: I writing to confirm that the MSI-X setting was causing the driver to hang. Changing my streaming FIFO design back to MSI interrupts resolved my issue. 




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