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Registered: ‎07-08-2019

DMA/Bridge Subsystem for PCIe example design

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DMA/Bridge Subsystem for PCIe example design does not work for 2018.2 but works for 2017.3.

Some module does not work.

 

DMA_20182.jpg
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Registered: ‎07-08-2019

Re: DMA/Bridge Subsystem for PCIe example design

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Status as of now:

 

1) Version Changed to 2019.1 is working

2) Project created in 2017.3 and open in 2018.2.2 without IP ugrading is working.

I can move ahead with my work. Would like to thank Garethc for his support.

Following things are not working

1) Creating project in 2018.2.2, and opening IP example design does not work.

2) Project created in 2017.3 and open in 2018.2.2 with IP ugrading is not working.

 

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Moderator
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Registered: ‎06-29-2011

Re: DMA/Bridge Subsystem for PCIe example design

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Hi dhaval.shah1@tcs.com 

I have a few questions.

  1. How did you move from version v2017.3 to v2018.2. The supported flow is to simply open the v2017.3 project in v2018.2 and let the vivado tools update everything. Then run repost_ip_status and upgrade the IP in the new v2018.2 project. In application menu, Report -> Report IP Status
  2. Are you using Verilog or VHDL, note that the example design is supported in Verilog and VHDL may show problems across versions. Please see the IP Facts Table on Page 6 of PG195.
  3. Have you tried creating a brand new XDMA out of the box example design project in v2018.2, does this show the same behaviour?
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Kind regards,
Gareth
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Registered: ‎07-08-2019

Re: DMA/Bridge Subsystem for PCIe example design

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I have a few questions.

  1. How did you move from version v2017.3 to v2018.2. The supported flow is to simply open the v2017.3 project in v2018.2 and let the vivado tools update everything. Then run repost_ip_status and upgrade the IP in the new v2018.2 project. In application menu, Report -> Report IP Status ANSWER: I had not done this . I followed step 3
  2. Are you using Verilog or VHDL, note that the example design is supported in Verilog and VHDL may show problems across versions. Please see the IP Facts Table on Page 6 of PG195. ANSWER. Using verilog only
  3. Have you tried creating a brand new XDMA out of the box example design project in v2018.2, does this show the same behaviour? ANSWER Yes
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Xilinx Employee
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Registered: ‎08-02-2007

Re: DMA/Bridge Subsystem for PCIe example design

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it is better to regenerate the example design in a new vivado

some IPs becides xdma IP also upgraded in new Vivado

it the old IP in your case bram_axi_contr_14.0 may have upgraded to v 15 for example , so there is no old version in the new vivado core 

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Registered: ‎07-08-2019

Re: DMA/Bridge Subsystem for PCIe example design

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Can you explain what new vivado means

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Re: DMA/Bridge Subsystem for PCIe example design

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Tried this 

  1. How did you move from version v2017.3 to v2018.2. The supported flow is to simply open the v2017.3 project in v2018.2 and let the vivado tools update everything. Then run repost_ip_status and upgrade the IP in the new v2018.2 project. In application menu, Report -> Report IP Status

But following issues pop up.

1) BRAM controller not working, that error reported continues

2) In board.v, get error "PL_SIM_FAST_LINK_TRAINING is not declared under prefix inst [/home/dhavalK/xdma_0_ex/imports/board.v:87"

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Registered: ‎07-08-2019

Re: DMA/Bridge Subsystem for PCIe example design

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Commentong that lines is logically incore
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Moderator
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Registered: ‎06-29-2011

Re: DMA/Bridge Subsystem for PCIe example design

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Hi dhaval.shah1@tcs.com 

I am sending you a EZMove mail for you to send me on your project so I can text this locally. Can you use the Archive project option to archive your project and send to me, e.g. File -> Project -> Archive

This will create a .zip of the project that you can send to me and I can test locally.

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Kind regards,
Gareth
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Re: DMA/Bridge Subsystem for PCIe example design

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Sure.
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Re: DMA/Bridge Subsystem for PCIe example design

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Hi dhaval.shah1@tcs.com 

I was able to replicate this and my investigations found that this is a known issue with v2018.2.2 where a few pre-compiled IP libraries are missig in the install area.

This is detailed in AR:71710 (lin below) and there is directions on how to manually regenerate the missing xsim libraries and work around this issue.
Note that this is fixed in the v2018.3 release.

AR:71710: 2018.2.2 Vivado - Some pre-compiled IP libraries for Vivado Simulator are missing in the install area
https://www.xilinx.com/support/answers/71710.html

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Gareth
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Registered: ‎07-08-2019

Re: DMA/Bridge Subsystem for PCIe example design

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Hi ,

 

I had removed the AXI BRAM , I am getting following error.

ERROR: [VRFC 10-93] PL_SIM_FAST_LINK_TRAINING is not declared under prefix inst [/home/dhavalK/xdma_0_ex/imports/board.v:87]

Also I am running the commands you mentioned, it is  more than a hour command was still running

 

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Registered: ‎06-29-2011

Re: DMA/Bridge Subsystem for PCIe example design

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Hi dhaval.shah1@tcs.com 

Why have you removed the AXI BRAM? You do not need to do this and need to just recompile the libraries for XSIM and point to these in the Vivado project.
Can you revert back to an out of the box example design and run the commands as per the details in the AR:71710?

Recompiling the libraries will take some time. It will be dependent in the machine being etc. At the moment I am doing a test with one of our Linux enviroments to see how long it takes.

Also if you note this issue is resolved in v2018.3 so if you move to that version you will not see this issue at all. Can you move to v2018.3?

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Gareth
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Re: DMA/Bridge Subsystem for PCIe example design

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Hi dhaval.shah1@tcs.com 

I have used the original project that your sent me and ran the commands in AR:71710 and this works and the simulation enviroment opens with no errors. So this will work if you need to stay with v2018.2.2

Recompiling the libraries tool my Linux enviroment 52 minutes to complete.

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Gareth
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Registered: ‎07-08-2019

Re: DMA/Bridge Subsystem for PCIe example design

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Want to  use PCIe EP connected to AXI interconnect as DUT and Root complex as Testbench, hence did the same. 

I ran the first command and was here around hour, seeing on the next day process seemed to be killed. Anyways will start new one

Migration: Migrated to latest 2019.1 and its working as expected. Thanks for this suggestion.

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Registered: ‎07-08-2019

Re: DMA/Bridge Subsystem for PCIe example design

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Status as of now:

 

1) Version Changed to 2019.1 is working

2) Project created in 2017.3 and open in 2018.2.2 without IP ugrading is working.

I can move ahead with my work. Would like to thank Garethc for his support.

Following things are not working

1) Creating project in 2018.2.2, and opening IP example design does not work.

2) Project created in 2017.3 and open in 2018.2.2 with IP ugrading is not working.

 

View solution in original post

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Registered: ‎07-08-2019

Re: DMA/Bridge Subsystem for PCIe example design

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3) Running the commands in AR:71710 takes more longer to me 2.15+ hrs and still running so I am not counting this in solution
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Registered: ‎11-13-2018

Re: DMA/Bridge Subsystem for PCIe example design

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Where did you get this example design?

Brad

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Re: DMA/Bridge Subsystem for PCIe example design

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Hi @bhall0107 

This is using the example design that is provided with the XDMA IP. If you look at PG195 in Example Design Chapter 6 on Page 97 you will see that for various configurations we have built in example designs.

Many of the Xilinx IP deliver example design projects which consist of top-level logic and constraints that interact with the created IP customization. These example designs also typically come with an example test bench to help simulate the design.

To open an example design project for an IP in either a standard project or a Manage IP project, select the IP customization in the IP sources tab, then right-click and select Open IP Example Design from the context menu. The Open IP Example Design dialog box will open for you to specify the location. The project is called <ip_name_ex>. In an IP Integrator block design, either select the IP in the IP Sources or access the IP directly from the block design and use the same procedure as above and right-click and select Open IP Example Design.

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Don’t forget to reply, kudo, and accept as solution.
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Kind regards,
Gareth