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Observer
Observer
1,052 Views
Registered: ‎02-20-2014

DMA/Bridge Subsystem for PCIe

Hi,

 

I'm trying to make a simple setup work on a ZCU106 board. I've attached a screenshot. I configured the DMA/Bridge Subsystem for PCIe in Bridge mode and I want to run it exclusively in MSI-X mode.
Questions so far that I could not answer from looking at the PG194/PG195 etc

1) Do I need to hook up the S_AXI_LITE port? The MSI-X table and PBA seem to get populated by the OS without

2) Do I need to write the registers in table 2-37 (PG194) to make multiple MSI-X work? One for S2MM and one for MM2S?

3) Is there something generally wrong with my setup to make the AXI DMA work? I've done some chipscopeing and I can depending on the exact configuration and machine I plug it into make a single MM2S transfer work, however I get a 'ghost' MSI-X from the MM2S channel and none after that. I've also had (in another experiment) hooked up an AXI Data Fifo between S2MM / MM2S to make sure there's enough room.

4) Is the following verilog code to generate MSI/MSIX requests sensible? (sorry indents seem to get messed up)

 

module irq_to_msi_req
(
input clk,
input rstn,
input [N_IRQS-1:0] irq,
input [N_IRQS-1:0] msi_ack,
input msi_enabled,
input msix_enabled,
output [N_IRQS-1:0] msi_req
);
parameter N_IRQS = 2;

wire use_ack = msi_enabled || msix_enabled;
wire rst = ~rstn;

reg use_ack_reg;
always @ (posedge clk)
use_ack_reg <= use_ack;


reg [N_IRQS-1:0] last_irq;
always @ (posedge clk)
last_irq <= ~rstn ? 'd0 : irq; 


wire [N_IRQS-1:0] int_req;
reg [N_IRQS-1:0] msi_req_int;

genvar i;
for (i = 0; i < N_IRQS-1; i = i +1) begin
assign int_req[i] = ~last_irq[i] && irq[i]; 

always @ (posedge clk)
if (rst)
msi_req_int[i] <= 1'b0;
else
msi_req_int[i] <= msi_ack[i] ? 1'b0 : msi_req_int[i] || int_req[i];
end

assign msi_req = ~use_ack ? irq : msi_req_int;
endmodule

Any pointers would be welcome, I've been beating on this for quite a while,

 

Moritz

system.png
address-map.png
bars.png
pcie.png
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Xilinx Employee
Xilinx Employee
976 Views
Registered: ‎08-02-2007

1S_AXI_LITE can be used if you need to config the core but it is optional

2 You will need to wirte registers

3 have you checked if the MSI  control reigsters are correctly configuredby  host

you can run lspci for sure

4 timing of msix is address  in figure 3-13 in pg194

 

MSI_ENABLE is acctually an output witch is the same  of the  msi enable in config space

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Observer
Observer
965 Views
Registered: ‎02-20-2014


@liy wrote:

2 You will need to wirte registers


So just to confirm: the core defaults to usr_irq_req[3:0] -> msi vector 0?
By writing register 0x2080 to 0x03020100 I map them such that usr_irq_req[0] causes MSI-X 0 to be triggered (i.e. what the OS configures for MSI-X 0), usr_irq_req[1] causes MSI-X 1 to be triggered etc ...?

 

For usr_irq_req[7:4] I would write to 0x2084 with 0x07060504?

  

Thanks,

 

Moritz 

 

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