08-06-2018 01:57 PM
Is there any equivalent for the DMA/Bridge subsys for PCIE IP that is offered for the Zynq US+ XCZU7EV, for the XCZU9EG that's on the ZCU102 dev board? There's a RTL PCIE block but it's not a complete solution. Is there any code out there that would give me the equivalent of that hard PCIE block that's in the 7EV? I wanted to test out a 7EV PCIE root design but I only have a ZCU102 dev board available.
08-06-2018 07:00 PM
Do you want to use PCIE DMA with PS PCIE
Have you checked out http://www.wiki.xilinx.com/XAPP1289+PCIe+Root+DMA
08-07-2018 10:46 AM
Yes, I did. I need to implement the PCIe in the PL, not the PS, because I will be using the GTs in the PS fabric for other things. Also need the Gen 3 speed that the PL GTs offer. But thanks for responding.
08-22-2018 08:56 AM