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Observer
Observer
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Registered: ‎08-20-2019

DMA/Bridge subsystem for PCI Express drops blocks of data

Hi,

 

I'm currently using the DMA/Bridge subsystem for PCI Express (4.1) in Vivado 2019.1 on a Zynq Ultrscale + board (attached). My host machine is reading data from my fpga design fine although blocks of data go missing time to time? I know this as I am passing incrementing data from the fpga to host machine application. See design attached. Any debugging ideas welcome. I am using the driver from here on the host machine: https://www.xilinx.com/support/answers/65444.html

Thank you for any help in advance.

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