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Participant
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Registered: ‎11-14-2018

DMA PCIe cannot pass data to kernel

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I have PCIe working coming from my Linux driver (at least the simple test I've setup) but getting data into the kernel has stumped me.

Using simple iowrite64 or writeq / read I can read and write data into my device from my kernel driver without a problem. To try and work the other direction I want to use the kernels dma library. Reading through PG194 I found that a lot of examples seem out of date. They reference that in the AXI: BARs menu there should be 3 fields per bar (reference page 64 of the documentation) but when I pullup the IP in my design I find only 1 field. Aperture base and high address are missing leaving me with only the AXI to PCIe translation entry.
Reading around I found that these fields have been moved to the address editor which makes sense, is this correct?

From there I look into the AXI to PCIe translation field and realize, well if my module is running at boot I cannot possibly know what this value will be pre synthesis. Sure enough the documentation also notes this and has pointed me to page 44 (AXI Base Address Translation Configuration Registers). Here is where I think I am going wrong because there are a few questions I need to answer that I cannot determine.
1. What do I place in these fields? Right now I am working with taking the handle produced by dma_alloc_coherent(...,handle...) and passing it via cpu_to_le64(). Is this the correct value for this field?
2. How do I input this value? My assumption is a simple AXI Write starting at address 0x208 on the AXI_CTL interface will do the trick.
3. Is there some confirm field I am missing? Once I write to the AXI_CTL interface I assume that any future writes within the assosciated BAR address space on AXI (not CTL) will apply the translation as shown in examples on page 64-68. Is there an additional step I have missed here?
4. Is there some way to confirm/identify what cpu/pci address space was written to in the end. Right now I am assuming the BAR translations are working but I have no way to verify this.
Assuming I did not flub something above am I possibly grabbing data from the dma I have allocated incorrectly?
For now what I do is take the return from the ret_mem = dma_alloc_coherent which I treat as a void * and cast to a structure of my choosing. From there I just try and read bytes out of the struct but they all seem to return garbage memory or at least nothing that I tried to pass on my PCI bus. 

If you have any advice on even a portion of this I would greatly appreciate it because I am at head banging into desk levels of stumped right now. 

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Participant
Participant
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Registered: ‎11-14-2018

Found out the problem was how I was passing the dma_handle (bus address) to the FPGA. 

Here is what I found works.
dma >> 32 goes into 0x208
dma & 0xFFFFFFFF goes into 0x20C

I mistakenly believed that cpu_to_le64 was doing this but that was me mixing up byte orders. 

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Highlighted
Participant
Participant
512 Views
Registered: ‎11-14-2018

Found out the problem was how I was passing the dma_handle (bus address) to the FPGA. 

Here is what I found works.
dma >> 32 goes into 0x208
dma & 0xFFFFFFFF goes into 0x20C

I mistakenly believed that cpu_to_le64 was doing this but that was me mixing up byte orders. 

View solution in original post

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