01-17-2017 01:58 PM
I'm using the DMA Subsystem IP v3.0 (Rev 1) with Vivado 2016.4 for C2H transfers using AXI4-Stream interface and Descriptor Bypass port.
When two transfers are close (less than 20 ms) only 64 bytes of the second message are transfered to host memory. If the interval is longer than 20 ms (approximately), the second message is transfered completely.
I have checked the design with ILA core and both messages are loaded correctly to the DMA core through the s_axis_c2h interface. My design is loading a new descritor when it has new message ready to transfer and then it asserts s_axis_c2h_tvalid and waits until s_axis_c2h_tready goes high to send the following tdata values. The port c2h_dsc_byp_ready remains asserted during the whole operation.
The channel status register (0x40) doesn't report any issue. It keeps value 0x1 (only busy bit is set).
I had the issue with KCU105 board and another board with a xcku35 device, both using PCIe Gen3 x8.
Can anyone give me any help?
02-15-2017 06:51 AM
It was actually a bug in my software that caused this behavior. The DMA IP is working fine.
11-02-2017 01:58 PM
Can you share any details on how you drive the bypass descriptor port? What values do you set for the src and dst addresses, and how do you drive the AXIS Tlast signal?
I tried to get this AXI4-STREAM to work via normal (non-bypass) however I cannot get it to work. So is that why you chose the bypass method?
11-06-2017 03:09 AM
please open a separate thread as your issue is different
Desc bypass is used to gain throughput by avoid descriptors to be written from host machine .
Are you trying it on xilinx eval board or your own board?
please generate the AXi stream example design in 2017.3 vivado for your target device and test it using the latest AR65444 drivers available.