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Visitor
Visitor
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Registered: ‎03-12-2017

DMA Subsystem Descriptor Bypass questions

Xilinx community,

 

I am new to working with DMAs and have some questions about operating the DMA subsystem in descriptor bypass mode. I built a project that uses the DMA/bridge subsystem for PCI express and custom logic that loads the C2H descriptor bypass port when a data source on the FPGA has data to send to the CPU memory. I am using an ILA to monitor the AXI bus and all other signals of interest. When I enable the FPGA to start transferring data all of the signals on the ILA look correct.  Data is being transferred over the AXI bus from the address specified by the source address descriptor. But.... I have no idea where the data is going. Which leads to my questions.

 

1. How is the destination address descriptor mapped back to the CPU memory? What do I need to do on the Linux side to access the data that was transferred? Does the xdma driver need to be modified to work with descriptor bypass mode?

 

2. I am only interested in C2H transfers. Do both the C2H and H2C descriptor bypass ports need to be enabled for descriptor bypass mode to work as is done in the example project?

 

3. My project involves transferring real-time data from multiple data sources from the FPGA to the CPU memory. Is descriptor bypass mode the fastest way to transfer data from the FPGA to CPU memory? Another option would be to have the FPGA set an interrupt when a data source has data to send then have the CPU initiate the data transfer. I would like to hear some opinions on this.

 

I am using Vivado 2017.2, DMA/Bridge subsystem for PCI express version 3.1 and the xdma driver provided by Xilinx in the AR65444 answer. I did build the example projects not using descriptor bypass in PG195 and successfully used the "dma_to_device" and dma_from_device" scripts. The "dma_from_device" script did not work with descriptor bypass mode which I expected. I also built the descriptor bypass example and it seemed to work i.e. the "channel completed descriptor count" incremented but I could not access the data.

 

Thanks for your help.

 

Paul

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Adventurer
Adventurer
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Registered: ‎11-24-2017

Hello @pkuna,

 

I have quite similar needs like you. I'm using DMA subsystem for PCIe, and I only need C2H transfer. I also need descriptor bypass but unlike you, I'm using AXI4-Stream interface insteaad of AXI-Memory Mapped.

 

Were you able to resolve your problem? Are you willing to share your project and custom logic with me? That would be a great starting point for me!

 

Thanks in advance for your time and effort.

 

Sincerely,

Bojan.

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Observer
Observer
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Registered: ‎06-29-2018

Hi,
I have a similar requirement like yours, but with an additional requirement of having one channel with Descriptor Bypass and one with normal DMA mode of operation.
The XDMA is working fine when i generate the core with only one channel without Descriptor BYpass interface, read write transfers are happening from Host using dma to device and dma from device scripts. However the scripts are not working when i enable second channel that is configured for DEscriptor Bypass. any help is much appreciated.
Also what configuration has to be done from RTL side to DMA for descriptor bypass cases.
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Moderator
Moderator
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Registered: ‎05-02-2017

hi @shahbaz_coreel @pkuna 

Thanks for contacting xilinx  forums ,

I see your looking for sample code , you can  generate the example design with the AXI4-Memory Mapped with Descriptor Bypass Example in vivado.

When Descriptor bypass mode is enabled, the user logic is responsible for making descriptors and transferring them in descriptor bypass interface. Mapped design with descriptor bypass mode enabled. You can select which channels will have
descriptor bypass mode. When Channel 0 of H2C and Channel 0 C2H are selected for Descriptorbypass mode, the generated Vivado example design has descriptor bypass ports of H2C0 andC2H0 connected to logic that will generate only one descriptor of 64bytes. The user is responsible for developing codes for other channels and expanding the descriptor itself.

 

Let me know your inputs

 

 

 

Regards
Chandra sekhar
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Observer
Observer
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Registered: ‎06-29-2018

Hi,

I had generated the example design with descriptor bypass mode enabled and saw the codes. I have built upon that logic to support multiple descriptor loading based on register configurations.

In the example design, I did not understand how the run bit for the H2C engine and C2H engine is in the control register is handled.

Is the bit set from host side or the bit has to be set from the RTL side using the AXI-L slave interface for XDMA configuration, also can we keep the run bit always set, I want the engines to be ready always to take the descriptors as and when we load it?

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Observer
Observer
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Registered: ‎06-29-2018

wherever I see the queries on descriptor bypass cases for XDMA in Xilinx forums, the reply from XiIlinx moderators remains same

"Thanks for contacting Xilinx  forums,

I see you are looking for sample code, you can generate the example design with the AXI4-Memory Mapped with Descriptor Bypass Example in vivado.

When Descriptor bypass mode is enabled, the user logic is responsible for making descriptors and transferring them in the descriptor bypass interface. Mapped design with descriptor bypass mode enabled. You can select which channels will have
descriptor bypass mode. When Channel 0 of H2C and Channel 0 C2H are selected for Descriptorbypass mode, the generated Vivado example design has descriptor bypass ports of H2C0 andC2H0 connected to logic that will generate only one descriptor of 64bytes. The user is responsible for developing codes for other channels and expanding the descriptor itself."

 

Please provide further support..!!

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