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Observer laurencebarker
Observer
552 Views
Registered: ‎05-27-2018

DMA/bridge system on Artix 75: fails timing when compile

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I am a relatively new FPGA designer. I'm using vivado 2018.3 and targeting an Artix device XC7A75TFGG484-1 or XC7A75TFGG484-2. My design has the Xilinx IP "DMA/bridge system for PCIe 4.1".

The project has a constraints file with timing constraints that were created using the timing wizard. There is only one constraints file in the design sources and it has my pin constraints (generated by me through editing the elaborated design) and wizard generated timing constraints. It includes definitions for the 125MHz and 250MHz clocks internal to the PCI express core. 

I have created a design in the Artix 75 with a software defined radio application (clocked at 122.88MHz) and a DMA/Bridge subsystem for PCI express. When I implement the project, I am getting several failures to meet timing constraints internal to the PCIe DMA core. These are in these groups:

intra-clock paths - clk_250mhz_Gen

inter-clock paths:

clk_125mhz to clk_250mhz_Gen

clk_125mhz_Gen to clk_125mhz

 

(when I ran the timing constraints wizard, it added these clock groups and they are listed in my constraints file:

create_generated_clock -name clk_125mhz_Gen -source [get_pins andromeda_top_i/PCIe/xdma_0/inst/andromeda_top_xdma_0_0_pcie2_to_pcie3_wrapper_i/pcie2_ip_i/inst/inst/gt_top_i/pipe_wrapper_i/pipe_clock_int.pipe_clock_i/pclk_i1_bufgctrl.pclk_i1/I0] -divide_by 1 -add -master_clock clk_125mhz [get_pins andromeda_top_i/PCIe/xdma_0/inst/andromeda_top_xdma_0_0_pcie2_to_pcie3_wrapper_i/pcie2_ip_i/inst/inst/gt_top_i/pipe_wrapper_i/pipe_clock_int.pipe_clock_i/pclk_i1_bufgctrl.pclk_i1/O]
create_generated_clock -name clk_250mhz_Gen -source [get_pins andromeda_top_i/PCIe/xdma_0/inst/andromeda_top_xdma_0_0_pcie2_to_pcie3_wrapper_i/pcie2_ip_i/inst/inst/gt_top_i/pipe_wrapper_i/pipe_clock_int.pipe_clock_i/pclk_i1_bufgctrl.pclk_i1/I1] -divide_by 1 -add -master_clock clk_250mhz [get_pins andromeda_top_i/PCIe/xdma_0/inst/andromeda_top_xdma_0_0_pcie2_to_pcie3_wrapper_i/pcie2_ip_i/inst/inst/gt_top_i/pipe_wrapper_i/pipe_clock_int.pipe_clock_i/pclk_i1_bufgctrl.pclk_i1/O]
set_clock_groups -logically_exclusive -group [get_clocks -include_generated_clocks clk_125mhz_Gen] -group [get_clocks -include_generated_clocks clk_250mhz_Gen]

 

)

 

The DSP side of the project is OK: I have had some timing failures, but I understand the design and what I need to do to fix them. Mostly these are gone. 

My design uses 2/3 of the block RAM resources (62 block RAMs) in the FPGA: this might be an issue, because the DMA core uses quite a lot of memory. 

 

My questions are:

1. Should I have also included a DMA/bridge core specific constraints file; and if so where do I get it from. Or is it automatically included through instantiating the core. (PG195 page 86 says an XDC file with original, unmodified constraints needs to be used; it doesn't identify the file). (I can see from running report_compile_order -constraints that .XDC files for the PCIe core are already included)

2. Should I have allowed the timing wizard to create the 125MHz and 250MHz clock definitions, or are all those handled by constraints that belong to the PCIe core?

 

 

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1 Solution

Accepted Solutions
Moderator
Moderator
444 Views
Registered: ‎02-11-2014

Re: DMA/bridge system on Artix 75: fails timing when compile

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Hello @laurencebarker,

If you open the IP example design after you have the XDMA core configured exactly how you want it, then you can see what timing constraints we recommend for your IP.

Keep in mind, these smaller Artix7 devices are difficult to meet timing in. I can give you some recommendations for synth/implant settings to ease timing closure.

Please try the following impl strategies with the IP Example Design to verify timing  is passing:

opt_design -directive NoBramPowerOpt

place_design -directive AltSpreadLogic_low

phys_opt_design -directive AggressiveExplore

Thanks,

Cory

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3 Replies
Moderator
Moderator
445 Views
Registered: ‎02-11-2014

Re: DMA/bridge system on Artix 75: fails timing when compile

Jump to solution

Hello @laurencebarker,

If you open the IP example design after you have the XDMA core configured exactly how you want it, then you can see what timing constraints we recommend for your IP.

Keep in mind, these smaller Artix7 devices are difficult to meet timing in. I can give you some recommendations for synth/implant settings to ease timing closure.

Please try the following impl strategies with the IP Example Design to verify timing  is passing:

opt_design -directive NoBramPowerOpt

place_design -directive AltSpreadLogic_low

phys_opt_design -directive AggressiveExplore

Thanks,

Cory

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Don’t forget to reply, kudo, and accept as solution.
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Observer laurencebarker
Observer
427 Views
Registered: ‎05-27-2018

Re: DMA/bridge system on Artix 75: fails timing when compile

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Thank you. The reference design constraints were quite different from what the timing wizard added, and the design does now compile and meet timing for the DMA bridge. The lesson for me is: keep looking when at first I didn't find enough examples.

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Participant deepwavebill
Participant
331 Views
Registered: ‎08-09-2018

Re: DMA/bridge system on Artix 75: fails timing when compile

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I have a follow on question to this post. We have a custom board with a xc7a75T Artix part installed on it.

If I create a design with just the PCIe DMA core it works properly on the board via the loopback test. I have the core configured with two DMA AXI streaming channels.

However, when I include the PCIe DMA core in my complete design that also includes two JESD204 RX cores, two JESD204 TX cores, and two JESD204 PHY cores the loopback test no longer works.

The example design for just the PCIe DMA core just has two constaint files. I have pasted the constraint files below. I have included these constraints in my constraints file for the complete design. Place and route tells me that I am meeting timing, but I am worried that I do not have the PCIe DMA core fully constrained. Are their other constraint files that I need to include? Thanks.

xilinx_xdma_pcie_x0y0.xdc

###############################################################################
# Timing Constraints
###############################################################################

create_clock -period 10.000 -name sys_clk [get_ports sys_clk_p]

###############################################################################
# Physical Constraints
###############################################################################

set_false_path -from [get_ports sys_rst_n]

#########################################################################################################################
# End PCIe Core Constraints
#########################################################################################################################

dwd_car_bd_pcie_only_pin_def.xdc

set_property PACKAGE_PIN P25 [get_ports sys_rst_n]
set_property IOSTANDARD LVCMOS33 [get_ports sys_rst_n]
#set_property PACKAGE_PIN R25 [get_ports pcie_wake_l]
#set_property IOSTANDARD LVCMOS33 [get_ports pcie_wake_l]
#set_property PACKAGE_PIN R25 [get_ports pcie0_l0_clkreq]
#set_property IOSTANDARD LVCMOS33 [get_ports pcie0_l0_clkreq]
set_property LOC IBUFDS_GTE2_X0Y2 [get_cells refclk_ibuf]
set_property PACKAGE_PIN E11 [get_ports sys_clk_n]
set_property PACKAGE_PIN F11 [get_ports sys_clk_p]
# From xdma core .xdc constraint
set_property PULLUP true [get_ports sys_rst_n]
# NET "sys_rst_n" LOC = M20 | IOSTANDARD = LVCMOS33 | PULLUP | NODELAY ;
set_property CFGBVS VCCO [current_design]

# CPU reset , SW2
set_property PACKAGE_PIN U4 [get_ports CPU_RESET]
set_property IOSTANDARD LVCMOS25 [get_ports CPU_RESET]

# LED's
set_property PACKAGE_PIN M26 [get_ports LED0]
set_property IOSTANDARD LVCMOS33 [get_ports LED0]
set_property PACKAGE_PIN T24 [get_ports LED1]
set_property IOSTANDARD LVCMOS33 [get_ports LED1]
set_property PACKAGE_PIN T25 [get_ports LED2]
set_property IOSTANDARD LVCMOS33 [get_ports LED2]
set_property PACKAGE_PIN R26 [get_ports LED3]
set_property IOSTANDARD LVCMOS33 [get_ports LED3]

# PMOD test points
set_property PACKAGE_PIN P26 [get_ports pmod0]
set_property IOSTANDARD LVCMOS33 [get_ports pmod0]
set_property PACKAGE_PIN T22 [get_ports pmod1]
set_property IOSTANDARD LVCMOS33 [get_ports pmod1]
set_property PACKAGE_PIN R22 [get_ports pmod2]
set_property IOSTANDARD LVCMOS33 [get_ports pmod2]
set_property PACKAGE_PIN T23 [get_ports pmod3]
set_property IOSTANDARD LVCMOS33 [get_ports pmod3]

# AD9528 Signals
set_property PACKAGE_PIN N19 [get_ports clk_sysref_request]
set_property IOSTANDARD LVCMOS33 [get_ports clk_sysref_request]
set_property PACKAGE_PIN L23 [get_ports ad9528_clk_resetb]
set_property IOSTANDARD LVCMOS33 [get_ports ad9528_clk_resetb]
set_property PACKAGE_PIN P19 [get_ports ref_sel_clkgen]
set_property IOSTANDARD LVCMOS33 [get_ports ref_sel_clkgen]

# Add glbl clk for the ILA block
set_property PACKAGE_PIN N3 [get_ports glblclk_p]
set_property IOSTANDARD LVDS_25 [get_ports glblclk_p]
set_property PACKAGE_PIN N2 [get_ports glblclk_n]
set_property IOSTANDARD LVDS_25 [get_ports glblclk_n]

# SPIx4 Config Properties
set_property BITSTREAM.CONFIG.CONFIGRATE 50 [current_design]
set_property CONFIG_MODE SPIx4 [current_design]

 

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