We've encountered a rather strange problem with PCIe DMA (Xilinx DMA/AXI bridge subsystem). When we transfer packets longer then 80 bytes, all works fine, but when packets are 80 bytes long or shorter, data transfer occurs, but no interrupt on data receive is sent and the core stays in "busy" state. (H2C works, C2H doesn't)
About our test system: The DMA/AXI bridge subsystem (v4.0) core is configured to provide DMA service through AXI-stream interface. M_AXIS_H2C connected to S_AXIS_C2H through AXI4_Stream Data FIFO (in packet mode) forming data loopback. Vivado 2017.3.1, VCU118 with ES chip.
We've also tried Vivado 2018.2 with the same result.
The same happens when we take example design driver + example design FPGA configuration. With packets of 81 bytes (changed in the dma_streaming_test.sh) it works, when we change packet size to be 80 bytes or less it doesn't.
It turned out that it's not only short frames. We've found no system in packet length that hang DMA engine. For example, frames with lengths 512 and 136 bytes are transmitted, while 200, 150 Bytes frames hang DMA engine.
We also found out that there is no such problem with other xcku15p chip. I suspect that the problem is caused by the fact that we use ES (engineering sample) chip. Another option is that it is somehow related to the fact that we have problems with US+ chip and don't have them with US chip. Maybe PCIe IP cores are somehow different for US+ and US families.