03-01-2020 09:25 PM
When i am compiling my project, i am getting the error as : [DRC 23-20] Rule violation (RTSTAT-1) Unrouted net - 2 net(s) are unrouted. The problem bus(es) and/or net(s) are DUT1/PCIE_RF_bus_i/axi_pcie3_0/inst/pcie3_ip_i/inst/gt_top_i/pipe_wrapper_i/pipe_lane.pipe_quad.gt_common_enabled.gt_common_int.gt_common_i/qpll_wrapper_i/int_qplloutclk_out, DUT1/PCIE_RF_bus_i/axi_pcie3_0/inst/pcie3_ip_i/inst/gt_top_i/pipe_wrapper_i/pipe_lane.pipe_quad.gt_common_enabled.gt_common_int.gt_common_i/qpll_wrapper_i/int_qplloutrefclk_out.
how to resolve this issue?
03-03-2020 07:26 AM
Please take a look at AR:65502 that provides details on how you can initially debug this and check if the workarounds work or you.
03-09-2020 02:33 AM
I am using the PCIE and aurora interface in same quad. i am generating the project using vivado 2015.2. i am getting error which generating the bitstream. when i see pcie its have GTH_common and qpll inside the ip which i am not able to change. i have aurora interface i tried to give clock to the interface from adjacent tile because PCIe ip is not providing any reference clock output. i am not able to generate the bitstream. how to resolve this issue?
03-10-2020 02:12 AM
Please create a new post if you are seeing another issue from your original post.