cancel
Showing results for 
Show  only  | Search instead for 
Did you mean: 
407 Views
Registered: ‎07-24-2019

DRC ERROR

Hello Sir,

 

              When i am compiling my project, i am getting the error as : [DRC 23-20] Rule violation (RTSTAT-1) Unrouted net - 2 net(s) are unrouted. The problem bus(es) and/or net(s) are DUT1/PCIE_RF_bus_i/axi_pcie3_0/inst/pcie3_ip_i/inst/gt_top_i/pipe_wrapper_i/pipe_lane[0].pipe_quad.gt_common_enabled.gt_common_int.gt_common_i/qpll_wrapper_i/int_qplloutclk_out[0], DUT1/PCIE_RF_bus_i/axi_pcie3_0/inst/pcie3_ip_i/inst/gt_top_i/pipe_wrapper_i/pipe_lane[0].pipe_quad.gt_common_enabled.gt_common_int.gt_common_i/qpll_wrapper_i/int_qplloutrefclk_out[0].

 

 

how to resolve this issue?

 

Regards,

Anuradha C

0 Kudos
3 Replies
garethc
Moderator
Moderator
325 Views
Registered: ‎06-29-2011

Hi anuradha.c@mistralsolutions.com 

Please take a look at AR:65502 that provides details on how you can initially debug this and check if the workarounds work or you.

https://www.xilinx.com/support/answers/65502.html

Thanks,

Gareth


------------------------------------------------------------------------------------------------

Don’t forget to reply, kudo, and accept as solution.

If starting with Versal take a look at our Versal Design Process Hub and our
Versal Blogs

------------------------------------------------------------------------------------------------
0 Kudos
288 Views
Registered: ‎07-24-2019

hello sir,

 

           I am using the PCIE and aurora interface in same quad. i am generating the project using vivado 2015.2. i am getting error which generating the bitstream. when i see pcie its have GTH_common and qpll inside the ip which i am not able to change. i have aurora interface i tried to give clock to the interface from adjacent tile because PCIe ip is not providing any reference clock output. i am not able to generate the bitstream. how to resolve this issue?

 

0 Kudos
garethc
Moderator
Moderator
268 Views
Registered: ‎06-29-2011

Hi anuradha.c@mistralsolutions.com 

Please create a new post if you are seeing another issue from your original post.

Thanks,

Gareth


------------------------------------------------------------------------------------------------

Don’t forget to reply, kudo, and accept as solution.

If starting with Versal take a look at our Versal Design Process Hub and our
Versal Blogs

------------------------------------------------------------------------------------------------
0 Kudos