06-03-2018 11:38 PM
We have a PCIe framework based elaborate control and data acquisition system where multiple FPGAs are connected to a CPU over PCIe. FPGAs use XDMA PCIe core for data transfer to user application and xdma driver running. The PC side is setup using Linux CentOS7. want to give a unique identifier to each FPGA which should be possible to change dynamically as per geographical location of the FPGA. I thought of using DSN field of extended configuration space for this purpose. The scheme works perfect when used with bare PCIE endpoint block but access to "cfg_dns" port is not provided in xdma subsystem which encapsulates pcie endpoint block. I am trying to achieve this using xdma with couple of alternatives as given below and both of them does not seem to solve my problem. For testing I am using KC705 and I am currently using Vivado 2018.1 to build my design.
1) Use configuration management interface to directly write the DSN space (0x41: dw aligned). Write operation does not work but read operation works. It seems that the core terms this config space as read only. Absence of read-only override signal has stopped me here.
2) Looking at the documentation, "Configuration Extend Interface" seemed like next best thing however the option to enable the interface is not available in the core wizard. Why ?
Is it possible to get access to DSN field with xdma ?
06-05-2018 01:35 AM
if it works with integrated block IP, i think it should work with XDMA as well.
the cfg_dsn ports may be buried internally, you can pull it up to the top level.
06-05-2018 02:08 AM
Thank you for your reply.
If I understand correctly, you are pointing to editing of XDMA top module for this. If yes, I have already tried this out and, I could edit the top module of XDMA to set the desired DSN. But I don't know if one can add a port to the core, since the *.stub.v/vhd files seemed to be auto-generated. If you could point me to the documentation for that, it could be helpful. Secondly, this project is being designed for CERN where we will using hundreds and hundred of these boards with different Xilinx devices (series7, UltraScale, UltraScale+ etc). Thus, editing XDMA core becomes a potential bottle neck for distribution and updates across devices/families.
Is there any alternative to editing the core manually ? Is it possible to add "cfg_dsn" port in the XDMA future release ?
Also, any opinion on "Configuration Extend Interface" ?
Appreciate your support.
08-22-2019 02:14 AM - edited 08-22-2019 02:15 AM
We have taken a note of this. We do recognize your use case. An official enhancement request has been filed. However, this doesn't guarantee the feature will be added in the IP. You could send a private message to me or @borisq at a later date to check on the status of the enhancement request.
02-26-2020 06:09 AM
is there any new development for the mentioned usecase? I've tried also to pull the cfg_dsn signal out but ran into the same issues with the generated stub files as mentioned before. They seem not to generate the cfg_dsn port although I added the port as good as I could to every verilog or VHDL file (*_core_top.sv, *_sim_netlist.v, *_sim_netlist_vhdl, *_stub.v, *_stub.vhdl). Vivado still throws an error, that no cfg_dsn port is defined. Is there a quick workaround, or is the information embedded in the encoded xdma_v3_0_vl_rfs.sv file?