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Explorer
Explorer
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Registered: ‎12-02-2012

Data alignment on AXI DMA bypass

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The AXI DMA bypass interface's data bus is whatever width the overall DMA interface is configured as, so it can be up to 512bits. In this case, are there any special rules about how data is aligned on this bus? Say I have a request that has an address of 0x4. Would the first word of the data be at data[7:0] or would it get bumped up to data[39:32]? With the corresponding shifts done to wstrb and etc.

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Xilinx Employee
Xilinx Employee
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Registered: ‎12-10-2013

Re: Data alignment on AXI DMA bypass

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Hi @zwabbit 

The AXI Master Bypass interface is an AXI4 compliant interface, with the AXI Burst Type set as b01 - INCR.  This means that the alignment is as you described. For an AWADDR 0x0004 (depending on AWSIZE of course) - would be [39:31] - and would be presented based on write strobes.

I would recommend review the AMBA AXI Base Specification - as it has several examples of addressing and location.

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Xilinx Employee
Xilinx Employee
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Registered: ‎12-10-2013

Re: Data alignment on AXI DMA bypass

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Hi @zwabbit 

The AXI Master Bypass interface is an AXI4 compliant interface, with the AXI Burst Type set as b01 - INCR.  This means that the alignment is as you described. For an AWADDR 0x0004 (depending on AWSIZE of course) - would be [39:31] - and would be presented based on write strobes.

I would recommend review the AMBA AXI Base Specification - as it has several examples of addressing and location.

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Explorer
Explorer
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Registered: ‎12-02-2012

Re: Data alignment on AXI DMA bypass

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Thanks for the pointer.

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