04-06-2011 09:51 PM
I am using the endpoint block plus for PCIe with ML506 board.
With the Pcitree tool I could able to identify the Xilinx board through PCIE feature and
I am able to read and write the Bars(memory present in the system).
These bars corresponds to the memory present in the application part of the Endpoint Block plus,
in the example design generated using the coregen,the size of the application memory is 8kB
Now suppose assume i have only 2 Bars implemented in the design say bar0 and bar1 these
corresponds to memory map of 4kB each in the application part of Endpoint block plus without
any overlapping of memory in between these bars. that is bar0 is mapped to 0-4kB & bar1 mapped to 4kB to 8kB
of memory of PCIe.
Now I want to have data transfer between these two bars.
So what changes need to be done to have a system in which the data tranfer from one bar to another
that is if any data present in the bar0 is changed the bar1 should also have the same changed value.
Any idea please...
Now if we want to increase the memory size of the PCIe(Endpoint Block Plus) that is 8kB in the example design higher size.how we can do it???
04-07-2011 10:23 PM
First Thank you for the reply............
My project is to establish a very high speed serial interface..........Here we are using 2 IP's namely Endpoint Block plus for PCIe & GTP RocketIO
I though using the Endpoint Block plus for PCIe IP to exchange the data from PC to FPGA memory and GTP RocketIO to establish the serial LInk,,,,,,,,,
In the GTP RocketIO we have the frame generator for giving the parallel data at the input of the GTP RocketIO Transceiver.
I Have established the serial link using only GTP RocketIO in which the frame generator generates the frames for the Transmitter & the Frame checker to check the received data at the receiver....
Now I thought of giving the frames(parallel data) to the GTP RocketIO from the memory of the Endpoint Block plus say this data corresponds to the Bar0 memory instead of the usuall GTP frame generator.......then the received data is given to the bar1.....so that we can check the signal integrity......of the serial communication using the above 2 IP's...................
04-12-2011 09:15 PM
04-16-2011 06:25 AM
one problem on fifo depth calculation..................
Here I have the application part of PCIe working at (62.5MHz or 125MHz clock) and we are getting 32bit of data per clock cycle.
means the data rate ia (62.5M*32=2Gbits/s=250Mbytes/s or 125M*32=4Gbits/s=500Mbytes/s)
But the clock rate of the GTP frame generator is (156.25MHz) and data rate is (156.25M*16=2.5Gbits/s=312.5Mbytes/s)
now I have to have a fifo between the PCIe application and the GTP ROCKETIO. what depth of fifo is good?
will it be good to have a application clock runing at 62.5MHz or 125Mhz which is better for this application..........
Can we can have the GTP runing at the different clock speed will it be good ???
Please suggest me............
you know both PCIE and GTP continously runs..........which fifo design method can be best ,,,,,,,,,,,,,,,,,,,,,,
04-20-2011 05:42 AM
you can deassert the trn_tsrc_rdy_n signal so that the PCIe core essentially slows down packets. You can use an "almost full" flag from your FIFO to slow down the PCIe interface from presenting data too quickly.