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santukms
Adventurer
Adventurer
8,299 Views
Registered: ‎09-15-2010

Data transfer using the PCIe.........


Hi,

I am using the endpoint block plus for PCIe with ML506 board.
With the Pcitree tool I could able to identify the Xilinx board through PCIE feature and
I am able to read and write the Bars(memory present in the system).
These bars corresponds to the memory present in the application part of the Endpoint Block plus,
in the example design generated using the coregen,the size of the application memory is 8kB

Now suppose assume i have only 2 Bars implemented in the design say bar0 and bar1 these
corresponds to memory map of 4kB each in the application part of Endpoint block plus without
any overlapping of memory in between these bars. that is bar0 is mapped to 0-4kB & bar1 mapped to 4kB to 8kB
of memory of PCIe.

Now I want to have data transfer between these two bars.
So what changes need to be done to have a system in which the data tranfer from one bar to another

 that is if any data present in the bar0 is changed  the bar1 should also have the same changed value.

 

Any idea please...

Now if we want to increase the memory size of the PCIe(Endpoint Block Plus) that is 8kB in the example design higher size.how we can do it???

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11 Replies
luisb
Xilinx Employee
Xilinx Employee
8,271 Views
Registered: ‎04-06-2010

Can you explain the purpose of doing this? Depending on the purpose, you will get different answers.
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santukms
Adventurer
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Registered: ‎09-15-2010

First Thank you for the reply............

 

My project is to establish a very high speed serial interface..........Here we are using 2 IP's namely Endpoint Block plus for PCIe & GTP RocketIO

 

I though using the Endpoint Block plus for PCIe IP to exchange the data from PC to FPGA memory and GTP RocketIO to establish the serial LInk,,,,,,,,,

In the GTP RocketIO we have the frame generator for giving the parallel data at the input of the GTP RocketIO Transceiver.

I Have established the serial link using only GTP RocketIO in which the frame generator generates the frames for the Transmitter & the Frame checker to check the received data at the receiver....

Now I thought of giving the frames(parallel data) to the GTP RocketIO from the memory of the Endpoint Block plus say this data corresponds to the Bar0 memory instead of the usuall GTP  frame generator.......then the received data is given to the bar1.....so that we can check the signal integrity......of the serial communication using the above 2 IP's...................

 

 

 

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santukms
Adventurer
Adventurer
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Registered: ‎09-15-2010

 Hi   ,

 

Is my explanation is clear for you...

Any idea's about how it can be Implementated......

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luisb
Xilinx Employee
Xilinx Employee
8,181 Views
Registered: ‎04-06-2010

This should be fairly straightforward. You should be able to map the content to BRAM. One of the BRAM will be for BAR0 and the other will be for BAR1.

I would recommend using both of the BRAMs in a dual port mode. That way you can read and write from them appropriately. You also mentioned that you're planning to have up to 8kB memory space. Remember that this will require multiple BRAMs to store the data for each BAR. I recommend using Block Memory Generator for this.

On the RX side of the PCIE core you're going to need to make module that will look at trn_rbar_hit_n to decide which BRAM to read or write to. If it's a read, then you're going to also generate a completion packet in your tx module with the data from BRAM. If it's a write, then you'll write to that address of the BRAM.

Another thing to note is that you're only going to need to grab the lower bits of the address from the TLP. The upper bits are more important for routing the packet. All you need to worry about are the lower bits that map out to the 4 or 8kB that you're planning to use.

Hope this helps...
santukms
Adventurer
Adventurer
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Registered: ‎09-15-2010

 

 

Thank you so much for your idea...

 

will try to implement it.......

 

 

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santukms
Adventurer
Adventurer
8,122 Views
Registered: ‎09-15-2010

 

 

hi

one problem on fifo depth calculation..................

 

Here I have the application part of PCIe working at (62.5MHz or 125MHz clock) and we are getting 32bit of data per clock cycle.

means the data rate ia (62.5M*32=2Gbits/s=250Mbytes/s or 125M*32=4Gbits/s=500Mbytes/s)

 

But the clock rate of the GTP frame generator is (156.25MHz) and data rate is (156.25M*16=2.5Gbits/s=312.5Mbytes/s)

 

now I have to have a fifo between the PCIe application and the GTP ROCKETIO. what depth of fifo is good?

 

will it be good to have a application clock runing at 62.5MHz or 125Mhz which is better for this application..........

Can we can have the GTP runing at the different clock speed will it be good ???

 

Please suggest me............

 

you know both PCIE and GTP continously runs..........which fifo design method can be best ,,,,,,,,,,,,,,,,,,,,,,

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Anonymous
Not applicable
8,105 Views

RC read BAR0, BAR1 and store the data. Then RC write to BAR0 with BAR1 data, to BAR1 with BAR0 data.

The application looks a little strange?

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luisb
Xilinx Employee
Xilinx Employee
8,082 Views
Registered: ‎04-06-2010

The depth of the fifo is going to depend on your application.  Remember you can throttle back the core PCIe core.

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santukms
Adventurer
Adventurer
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Registered: ‎09-15-2010

 

Hi ,

 

 

>Remember you can throttle back the core PCIe core

 

Can you please explain me in detail about this

please..................

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luisb
Xilinx Employee
Xilinx Employee
3,328 Views
Registered: ‎04-06-2010

you can deassert the trn_tsrc_rdy_n signal so that the PCIe core essentially slows down packets.  You can use an "almost full" flag from your FIFO to slow down the PCIe interface from presenting data too quickly.

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santukms
Adventurer
Adventurer
3,323 Views
Registered: ‎09-15-2010

thank you very much for the quick reply.............i will try..............it
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