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Observer
Observer
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Registered: ‎06-15-2018

Diminished PCIe Gen3 bandwidth

I am currently trying to design an architecture that allows for multiple master axi access points to DDR4 on the VCU108 Evaluation Kit using Vivado 2018.2. Typically for multiple axi access points, the axi interconnect is used to manage traffic and connections between the master and slave modules. For this application, we need to be able to access DDR4 using the PCIe/DMA Bridge Subsystem v4.0, but also with user logic either using a Microblaze or a custom axi peripheral.

 

Initially I was able to get a PCIe only design working rather quickly using the Xilinx drivers and measure a performance bandwidth of 6.4 GT/s at the host computer. The problems occur whenever I try to expand to allow for Microblaze access to the DDR4 as well. Just by adding the MicroBlaze to the axi interconnect that passes DDR4 traffic, our PCIe speeds diminish down to about 200 MT/s. I've removed the debug module for the MicroBlaze that I assumed was probably polling the DDR4 memory locations, and observed the MicroBlaze traffic to the axi interconnect using the ILA while the performance test was running, and the Microblaze isn't generating any bus traffic during the test, but still my PCIe speeds are reduced to about 2% of maximum. The block diagram shows my current design. Does the difference in master axi ports coming from the microblaze and xdma cause this diminished bandwidth? If so, would creating a custom axi peripheral with the same master axi ports as the xdma for the second access point allow for the full PCIe to DDR4 speeds?

pcie_dma_mb_ddr4.PNG
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Highlighted
Observer
Observer
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Registered: ‎06-15-2018

I've probed the output of the axi interconnect with just the XDMA connected during a write, and with the XDMA and a dummy connection to slave 2 during a write. I expected the signals to be delayed somewhat because of multiplexing on the axi interconnect, but some of the signals are inverted. Does anyone have an explanation for this?

 

The first image is of the axi interconnect output to the DDR4 with the XDMA only configuration.

The second image is of the axi interconnect output to the DDR4 with the XDMA and dummy input configuration.

run_test_good_write.PNG
run_test_bad_write.PNG
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