01-15-2015 10:22 AM
I have an embedded system that uses the "AXI Bridge for PCI Express GEN3 Subsystem". The PERST signal on the board is not connected to the dedicated FPGA pin so I disabled the use dedicated PERST routing option. This is failing now at the write_bitstream stage with the following error:
[Vivado 12-1411] Cannot set LOC property of ports, Could not legally place instance PCIE_PERST_L_IBUF_inst at AJ29 (IOB_X1Y168) since it belongs to a shape containing instance GEN_MB_SUBSYSTEM.mb_subsystem_wrapper_i/mb_subsystem_i/axi_pcie3_0/inst/pcie3_ip_i/U0/pcie3_uscale_top_inst/pcie3_uscale_wrapper_inst/PCIE_3_1_inst. The shape requires relative placement between PCIE_PERST_L_IBUF_inst and GEN_MB_SUBSYSTEM.mb_subsystem_wrapper_i/mb_subsystem_i/axi_pcie3_0/inst/pcie3_ip_i/U0/pcie3_uscale_top_inst/pcie3_uscale_wrapper_inst/PCIE_3_1_inst that cannnot be honored because it would result in an invalid location for GEN_MB_SUBSYSTEM.mb_subsystem_wrapper_i/mb_subsystem_i/axi_pcie3_0/inst/pcie3_ip_i/U0/pcie3_uscale_top_inst/pcie3_uscale_wrapper_inst/PCIE_3_1_inst. ["/group/cdc_ir/projects/xilinx-2000/vc730trig-3300/usr/keithf/IP5_keithf_2000_3300_tid05/HEAD/proj/chip_vcu130/build/board_top.xdc":1252]
It appears that there's an input buffer within the PCI bridge which is preventing using anything other than dedicated routing. Do you know if there is a way to solve this problem?
(using Vivado 2014.4)
01-20-2015 03:47 AM
Have a look at the below AR.
In latest releases i think the dedicated route is enabled so that the violation causes error.
I think you will have to work wit old core/tool to workaround this issue.
01-26-2015 08:25 AM
Thanks for your reply Kotir. Unfortunately the answer record mentioned actually refers to the PCIe Gen 3 integerated block. I have not had any issues with placement when disabling the dedicated routing in this block.
01-27-2015 04:11 AM
Axi PCIe Gen3 underlying uses the Gen3 hardblock.
It applies to Axi pcie gen3 also.