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Visitor isauzun
Visitor
8,449 Views
Registered: ‎06-17-2009

Does BMD design actually support interrupts?

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I am using latest BMD design (v1.1) with Endpoint Block Plus core v1.9.

 

It seems to me that the core never generates an interrupt in order to indicate end of DMA transfer. I have also monitored cfg_interrupt_n signal using chipscope, and it is never asserted.

 

When looking through BMD_INTR_CTRL.v source code file, I noticed that the interrupt is generated on following condition.

 

 --------------------

           if (mwr_done && !cfg_interrupt_rdy_n_i) begin

            wr_intr_n = 1'b0;
            wr_intr_assert_n = 1'b0;
            next_wr_intr_state = `BMD_INTR_WR_ACT;

          end else begin

            wr_intr_n = 1'b1;
            wr_intr_assert_n = 1'b1;
            next_wr_intr_state = `BMD_INTR_WR_RST;

          end

 

 --------------------

 

Is this actually right, since cfg_interrupt_rdy_n_i signal is asserted by the core AFTER an interrupt request?

 

Thanks,

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Visitor rr88
Visitor
9,848 Views
Registered: ‎02-26-2009

Re: Does BMD design actually support interrupts?

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Answer comes with good news. My interrupt work well now!

Software problems. The level sensitive interrupt input should be deasserted immediately after interrupt service routine is invoked. I did the deassertion in my user application interrupt routine. But this action was delayed too much to be ' immediate', which cause many more interrupts pending before user mode interrupt service triggered the deassertion of the interrupt request.    I should have read the WinDriver user's Manual more carefully. The chapter on 'Handling Interrupts' describes so clearly about how to make WinDriver do this job. Just tell it which bit position and which address in user memory space to trigger the deassertion of interrupt request.

Message Edited by rr88 on 09-01-2009 05:25 AM

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6 Replies
Visitor rr88
Visitor
8,197 Views
Registered: ‎02-26-2009

Re: Does BMD design actually support interrupts?

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I agree with you.

According to ug341.pdf, I think user logic should invoke an interrupt by asserting  wr_intr_n. Then wait for the core's acknowledgement, that is, the assertion of cfg_interrupt_rdy_n_i. After detecting a '0' on cfg_interrupt_rdy_n_i, user logic should deassert the wr_intr_n...

 

But the problem I'm facing is EVERYtime when I invoke an interrupt, my interrupt routine works 9 or 10 times, sometimes even more than 40 times.

 

SOMEBODY Help me!  & thanks

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Visitor rr88
Visitor
9,849 Views
Registered: ‎02-26-2009

Re: Does BMD design actually support interrupts?

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Answer comes with good news. My interrupt work well now!

Software problems. The level sensitive interrupt input should be deasserted immediately after interrupt service routine is invoked. I did the deassertion in my user application interrupt routine. But this action was delayed too much to be ' immediate', which cause many more interrupts pending before user mode interrupt service triggered the deassertion of the interrupt request.    I should have read the WinDriver user's Manual more carefully. The chapter on 'Handling Interrupts' describes so clearly about how to make WinDriver do this job. Just tell it which bit position and which address in user memory space to trigger the deassertion of interrupt request.

Message Edited by rr88 on 09-01-2009 05:25 AM

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Newbie renlf
Newbie
7,244 Views
Registered: ‎04-15-2010

Re: Does BMD design actually support interrupts?

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hello ! Do  you use ML507 ?? I  use WinDriver to generate my driver for the ML507 and implement the BMD read which  transfer datas to the main memory of a computer,now I am wondering that initiate a interrupt from the ML507 board to PC,but I don't know how to USE Windriver to help me realize the interrput,can I get any  number which I can contact to you ? my emai is renlf7886@yahoo.com.cn  ,Do wish to get help from you. I  am a graduate inschool ,this is my  design for graduation.
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Newbie renlf
Newbie
7,237 Views
Registered: ‎04-15-2010

Re: Does BMD design actually support interrupts?

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hello it's me again  I wonder in the Windriver ,when I need to deassert the interrupt,  which bit and Which register I will write ???
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Adventurer
Adventurer
7,189 Views
Registered: ‎01-29-2008

Re: Does BMD design actually support interrupts?

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Hi,

 

I face the same problem than renfl.

I do not use windriver but I use the linux driver provided by Xilinx.

 

When I use interrupt for a read or write DMA transfer, the interrupt is never deaserted by the FPGA design.

I try to reset the initiator in the interrupt handler, and also to disable interrupt for both read and write DMA operation in the DMA control  register.

But there is no effect, the interrupt is continuously firing.

 

So I don't really understant the solution proposed by rr88.

Do we need to modify the design : for instance by adding a register to stop interrupt.

Or it is just a software issue ? Maybe the driver provided by Xilinx do not handle interrupt in a good way.

 

Some informations :

The interrupt use by the linux kernel module (xbmd.ko) is shared, and seems not to be handled as a edge sensitive interrupt. An extract of my /proc/interrupts :

  0:         56    XT-PIC-XT        timer
  1:          2    XT-PIC-XT        i8042
  2:          0    XT-PIC-XT        cascade
  3:          3    XT-PIC-XT        ohci_hcd:usb1, ohci1394, xbmd

Maybe I need to "force" the kernel to handle this interrupt as edge sensitive.

 

Thanks for help

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Explorer
Explorer
5,253 Views
Registered: ‎02-17-2013

Re: Does BMD design actually support interrupts?

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Hi zben

Did you resolve your problem I have similar problem you can see my post in this link. 

I changed the number od id 0 to 4 because the 4 is availble but my computer plant and I need restart the pc. It's a problem with the variable gDev->irq who contains the value 0 when the programm call the function request_irq(). in my proc/interrupt the id 0 in unavaible. 

         CPU0            CPU1          CPU2         CPU3
0:     327720         273313        253628       286213         IO-APIC-edge           timer
1:              0                  0                2                0         IO-APIC-edge           i8042
4:              1                  0                1                1         IO-APIC-edge
8:              0                  0                0                1         IO-APIC-edge            rtc0
9:              0                  0                0                0         IO-APIC-fasteoi          acpi
12:            0                   1               3                0          IO-APIC-edge            i8042
16:            0                   0               0                0          IO-APIC-fasteoi uhci_hcd:usb3

 http://forums.xilinx.com/t5/New-Users-Forum/Xilinx-xapp1052-xbmd-ko-cant-load/m-p/339431#M5026

Best Regards. 

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