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evan172
Visitor
Visitor
9,566 Views
Registered: ‎08-28-2014

Does Xilinx IP support asynchronous reference clock and use SFP instead of PCIE cable?

Hi,

As PCIE cable is thick and not easy winding, we tried to use STP and fiber to instead of cable. In common design, EP reference comes from slot edge, and it's syncronous  with RC, and TX/RX is transfered with cable, now if use fiber, syncronous clock is not availble and want to use a local reference clock for input.

 

Does Xilinx IP  support asynchonrous reference clock well? Do you know cases like above? If yes, how to config the core? expect "the Slot Clock Configurationsetting in the Link Status Register must be disabled".

 

In document pg023_v7_pcie_gen3.pdf page 76 there are lines:

IMPORTANT: The most commonly used clocking methodology is synchronous clocking. All add-in card
designs must use synchronous clocking due to the characteristics of the provided reference clock. For
devices using the Slot clock, the Slot Clock Configurationsetting in the Link Status Register
must be enabled in the Vivado® IP catalog. See Clocking Requirements, page 79and the 7 Series
FPGAs GTX/GTH Transceivers User Guide (UG476) [Ref 7]for additional information regarding
reference clock requirements.

 

 

In our lab, we test gen1x4 example still using PCIE cable but with a local 100 Mhz asynchronous reference clock , using K7-325T FPGA, vivado 2014.02, it can link up, but not stable, the performance is 5 seconds linked up, then 5 seconds linked down, also tried other versions of vivado, like 2013.04, it can't link, and if configes to gen2x4 using vivado 2014.02, it failed to link up either.

 

Thanks.

 

 

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liy
Xilinx Employee
Xilinx Employee
9,561 Views
Registered: ‎08-02-2007

if you need to use async clock, please make sure the pcie_async_en is enabled in the code 

the recovered clock will be used to drive the pcs module 

PG023 is for Gen3 if you are using k7 , you will need to refer to pg054

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kotir
Scholar
Scholar
9,514 Views
Registered: ‎02-03-2010

Hi ,

 

In case of async design you should disable the ASPM and SSC these are mentioned in the AR 18329 (http://www.xilinx.com/support/answers/18329.htm )

 

The GT clocking module should satisfy the requirements of the PCIe standard.

Have a look at the below AR and PCIe spec

 

You should also look at this. http://www.xilinx.com/support/answers/44549.html

 

I would also suggest you to confirm if the clocking on your board is according to “4.3.7.2. Refclk Architectures”section  of PCIe 2.0 Base spec.

 

Regards,

KR

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