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ting.objective
Contributor
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Registered: ‎04-01-2013

Driver can not access the registers in the peripheral through AXI_PCIE

Hi everybody,

 

I create a project of XPS using BSB wizard, adding the PCI-Express Peripherial. A peripherial named axi2axi_interconnecter is added into the system automatically.

After downloading the bitfiles into FPGA, loading the PCI-Express driver written by myself, the linux can detect the PCI-Express device.  We can also access the memory in the AXI4 address domain, however, the registers in the peripherial can not be accessed by the driver even thought the address domain containing the registers is mapped to the BAR.

 

Can somebody tell me how the driver can access the registers in the peripherial by using the AXI_PCIE core?

 

Thanks in advance.

 

 

Ting
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kotir
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Registered: ‎02-03-2010

Hi ,

 

You may have to check if the mem, i/o and bus master bits are properly enabled in the command register.

Also check if any rules of Address boundary or packet formation rules are  violated.

 

If you are trying to 6 series devices, below ARs can be loooked for referance systems.

http://www.xilinx.com/support/answers/43371.html

http://www.xilinx.com/support/answers/43677.html

 

 

Regards,

KR

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ting.objective
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Registered: ‎04-01-2013

Hi kotir,

 

Thanks a lot for your reply.

Firstly, i not sure the location of the "command registers" you referred.

Secondly, I have checked the example design for ml605 and i can not find the difference between this and our projcet. built in edk 14.7.

 

I think you may not understand where is my problem because my poor description. Here I will give some figures to detail my problem.

 

1.  Use the axi2axi_connector default configuration (slave interface - axi4lite, master interface - axi4)

The ddr3 memory can be accessed by driver but registers resided in ip cores can not.

pic.png

2. Change the axi2axi_connector configuration (slave interface - axi4, master interface - axi4lite)

The registers resided in ip cores can be accessed by driver but not the ddr3 memory.

Slice 2.png

 

looking for your reply.

 

 

 

 

Ting
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kotir
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Registered: ‎02-03-2010

Hi ,

 

Commad register will bein the configuraiton space of the core.

 

Can you check the difference between the core address map for both the memory and IP with registers ?

 

I believe the AXI pcie will have two BARs one for accessing memory and another for IP with registers.

Do you see this in your project ?

 

Regards,

KR

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