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tejaallani
Observer
Observer
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Registered: ‎05-08-2018

FPGA XDMA device initiated C2H to Windows 10 HOST PC via PCIE to shared memory

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Hi,

    I have been following pg021 to setup a DMA. I wanted to know if the following scenario is possible:

  • Is it possible to have an application on Host PC and FPGA device share memory at host side, as far as I know without driver help it is not possible to get physical address in windows. Do Xilinx drivers provide any way to allocate a shared memory between user application and Xilinx PCIE device so that these devices can share the memory in Host?
  • If it is possible, I want to pass this allocated memory address to FPGA so that the device can write to this shared memory and raise an interrupt without Host CPU involvement.

Can anyone help if the above scenarios are possible and where to start with, I mostly am interested on the possibility of shared memory allocation at host side.

 

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bhall0107
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Registered: ‎11-13-2018

 Hi @tejaallani

I'm not sure that I'm able to answer your questions, but I wanted to share some resources that I think could help you find the answers and get a better understanding of how XDMA works. Maybe you've already seen them, but I hope it's helpful. 

https://www.xilinx.com/member/xdma_windows_driver/XDMA_Windows_Driver_SoftwareGuide.pdf
https://www.xilinx.com/Attachment/Xilinx_Answer_71435_XDMA_Debug_Guide.pdf
https://www.xilinx.com/support/documentation/ip_documentation/xdma/v4_1/pg195-pcie-dma.pdf

Good Luck!
Brad

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bhall0107
Adventurer
Adventurer
310 Views
Registered: ‎11-13-2018

 Hi @tejaallani

I'm not sure that I'm able to answer your questions, but I wanted to share some resources that I think could help you find the answers and get a better understanding of how XDMA works. Maybe you've already seen them, but I hope it's helpful. 

https://www.xilinx.com/member/xdma_windows_driver/XDMA_Windows_Driver_SoftwareGuide.pdf
https://www.xilinx.com/Attachment/Xilinx_Answer_71435_XDMA_Debug_Guide.pdf
https://www.xilinx.com/support/documentation/ip_documentation/xdma/v4_1/pg195-pcie-dma.pdf

Good Luck!
Brad

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tejaallani
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Registered: ‎05-08-2018

Thanks Brad, I looked at driver source code and observed that driver is allocating memory at host dma/pcie bridge mode and I just need to call read api to get the data.

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