06-26-2019 11:56 PM
I have used the linux drivers from AR65444 to communicate over the PCI bus between a host and an AC701 board. All of the scripts in the tests directory indicate that the test data is being sent back and forth successfully, so I am now trying to access the H2C data on the FPGA. I am using the ILA to probe the signals that I thought were carrying the received data, but the ILA is not showing what I expected.
My vivado project was created using "open IP example design" from the DMA Subsystem for PCIe core.
I have tried triggering on the signal m_axi_wready, which is from the "AXI Master Write Data Channel" part of the wrapper file, but it never triggers. First I tried triggering on the BRAM ready signal, but the ILA never triggered either.
I am probing m_axi_wdata. Am I looking at the wrong signals?
07-30-2019 10:50 AM
I'm not sure, I can't see any signals because the ILA never triggers. I thought I should be triggering on the m_axi_wready signal, is there a different one I should be triggering on?
07-31-2019 11:57 PM
It is strange that the signal does not work even though the driver test is successful. Please check the point of the probe. Also, see if the address is correct with awvalid.
The correct behavior can be seen in simulation.
08-06-2019 03:12 PM
I was able to see the data by triggering the ILA on m_axi_wvalid, and I confirmed that it matches the test data from the AR65444 example files.
09-06-2019 06:32 PM
I know you told me to make sure the address is correct, so I probed the m_axi_waddr signal. This address signal is always larger than the size of the block RAM that is being written to. How does this make sense? It seems to me that the address should go from 0 to 512 for a RAM with depth 512, but instead the address goes from 512 to 1024 to 1536 and so on.