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Visitor
Visitor
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Registered: ‎09-08-2009

Gated Clock in V5 PCIe Endpoint Block Plus v1.11 ?

Hi,

 

during bitgen of the PCIe Endpoint Block Plus example design which comes with the core I got the following

warnings about gated clocks:

 

 

Release 11.2 - Bitgen L.46 (lin)
Copyright (c) 1995-2009 Xilinx, Inc.  All rights reserved. 

...

WARNING:PhysDesignRules:372 - Gated clock. Clock net
   ep/BU2/U0/pcie_ep0/pcie_blk/SIO/.pcie_gt_wrapper_i/icdrreset<1> is sourced by
   a combinatorial pin. This is not good design practice. Use the CE pin to
   control the loading of data into the flip-flop.
WARNING:PhysDesignRules:372 - Gated clock. Clock net
   ep/BU2/U0/pcie_ep0/pcie_blk/SIO/.pcie_gt_wrapper_i/icdrreset<2> is sourced by
   a combinatorial pin. This is not good design practice. Use the CE pin to
   control the loading of data into the flip-flop.
WARNING:PhysDesignRules:372 - Gated clock. Clock net
   ep/BU2/U0/pcie_ep0/pcie_blk/SIO/.pcie_gt_wrapper_i/icdrreset<3> is sourced by
   a combinatorial pin. This is not good design practice. Use the CE pin to
   control the loading of data into the flip-flop.
WARNING:PhysDesignRules:372 - Gated clock. Clock net
   ep/BU2/U0/pcie_ep0/pcie_blk/SIO/.pcie_gt_wrapper_i/icdrreset<0> is sourced by
   a combinatorial pin. This is not good design practice. Use the CE pin to
   control the loading of data into the flip-flop.  

...

 

Is this a known problem ?

Can we ignore this warning ?

 

I used ISE 11.2 tool chain on 64bit Linux OS.

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Anonymous
Not applicable
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refer to pcie_blk_plus_ug341.pdf

 

This warning can be ignored.

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