I'm trying to use tandem PROM setting on the xdma subsystem for pci express 4.1 when flash a Kintex Ultrascale xcku060 fpga. Moreover, I am flashing the device via JTAG/Xilinx Usb. I have several questions:
The code for the top level is in VHDL, is that fine? I saw in documentation that it supposedly supports Verilog only.
When instantiating the PCIe xdma with the tandem setting, I see there are several new pins to assign/wire. I don't see descriptions anywhere in the related documentation that describe the startup ports. I do see that there is a section mentioning the importance of the startup block, so as to initiate the handshake to move on from the pcie configuration to the user application configuration of the bitstream. How should those ports be wired?
Within the xdc there are only constraints set for flashing via SPI/BPI. If I am flashing using JTAG/USB do I need to be concerned with these xdc settings? What xdc settings do I need to set?
Thank you all ahead of time, I'm relatively junior, especially when it comes to configuring these IPs