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Visitor pedminacar
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Registered: ‎06-05-2019

Help with DMA

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Hi

I'm new in this forum and right know I'm working in my master thesis. The goal of the thesis is to make parallel communication between FPGA and CPU. There is an application in my University which is necessary to make it run faster than it is now. So I've searched for how to make the communication and I discovered that I need a DMA module to receive and send data from/to the PC memory. I've been searching on the tutorials and datasheets and I can't find the answer for some questions I have. I know the DMA needs to create a TLP packet, to send information through PCI Express, so how does the DMA know which address to write or read on the PC memory? Is it necessary DRAM4 in my design? Forgot to mention that I have a VHDL file that is a controller that makes some calculations when that same file receives data, so what I thought was to make only one entrance and only one exit for data and each signal that I'm using is going to have the input and a output. I have to say that the VHDL file will be generated automatically so it can't have a dinamic amount of inputs or outputs.

The text is a bit confusing, but I don't know if I should say too much details about my thesis.

Thank you

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1 Solution

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498 Views
Registered: ‎06-21-2017

Re: Help with DMA

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You will probaby need to use some type of memory on the FPGA side of the DMA to buffer DMA blocks.  This could be the DDR RAM on the FPGA board, a BRAM or a FIFO.  Using the DDR will mean using the MIG (I think that's memory interface generator IP).  The BRAM can either be infered from your VHDL or added as an IP block.  A FIFO is usually added as IP, but it really isn't that hard to write your own.  Depending on your algorithm, you may want to use other IP.  There is a lot of IP included with Vivado.  You will need a licensed version of Vivado.  You may be able to get a license through your school.  The free version of Vivado does not support Virtex and I didn't see that the board comes with a license.  That is a full size, eight lane PCIe card.  Does your computer have a slot that can use this card?

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Registered: ‎06-21-2017

Re: Help with DMA

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Do you currently have a FPGA to processor PCIe link and you are just trying to add DMA, or are you starting from scratch and need to get a PCIe link up first?  What FPGA are you using.  Is it on an evaluation board?  Which one?

 

To answer some specific questions, there will be registers in the PCIe endpoint design (in the FPGA) that the processor will write to tell the endpoint the address of the DMA.

Visitor pedminacar
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Registered: ‎06-05-2019

Re: Help with DMA

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Hi

The board I will use is this https://store.digilentinc.com/netfpga-sume-virtex-7-fpga-development-board/

There is a video in Xilinx about using pcie, where they talk about DMA, DDR4, GPIO, all this in a design file. So what I want to do and I was hoping it could work is the following: Having a VHDL file with several signals (in my thesis it is petri nets places values) and I have a input for the places values and a output with also places values (after some calculation). So I need to put the right value in each signal (it can have thousands of signals), so my idea is stablish a rule where place 1, place 2, place 3, etc. are consecutive in memory (PC memory) and DMA by knowing where the part of the memory the values are, would be able to retrieve the values and put on the signals in my VHDL file. So that is where my struggle starts, since I can't find on the internet how DMA knows which address, let say, the place 1 value is in to be able to retrieve and send to VHDL file. So do I need, apart from the DMA, any other IP module?

Thank you

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499 Views
Registered: ‎06-21-2017

Re: Help with DMA

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You will probaby need to use some type of memory on the FPGA side of the DMA to buffer DMA blocks.  This could be the DDR RAM on the FPGA board, a BRAM or a FIFO.  Using the DDR will mean using the MIG (I think that's memory interface generator IP).  The BRAM can either be infered from your VHDL or added as an IP block.  A FIFO is usually added as IP, but it really isn't that hard to write your own.  Depending on your algorithm, you may want to use other IP.  There is a lot of IP included with Vivado.  You will need a licensed version of Vivado.  You may be able to get a license through your school.  The free version of Vivado does not support Virtex and I didn't see that the board comes with a license.  That is a full size, eight lane PCIe card.  Does your computer have a slot that can use this card?

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Visitor pedminacar
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493 Views
Registered: ‎06-05-2019

Re: Help with DMA

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Hi

The computer I'll use is from my University, so it will work with the card. But I still don't know the flow of working of DMA. I know the driver of the PC is responsible for the communication with the PCI express, but I don't know till what extent. The DMA needs to know where the info in the PC memory is, so it can retrieve and send information. Regarding the DDR4 module of Vivado, I still don't know how to access the info inside the module. The video I saw about DMA have a "exit" from the DDR4, but I don't know what the ports of that "exit" do exactly. So, how to read data from the DDR4?

Thank you for your time

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Registered: ‎06-21-2017

Re: Help with DMA

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There need to be registers in the design that the driver can write to to tell the DMA hardware in the FPGA what addresses on the PC's memory to get data from and write data to.  I haven't played with a PCIe DMA since my Spartan6 days, so I don't know exactly what the Vivado version of the PCIe design is like.  As I stated, you may or may not need to use the DDR RAM on the board.  It depends on your design.  If you want to know what the FPGA's interface to the on-board DDR RAM (not the PC's RAM) open Document Manager and look for the user's guide for the MIG or search the net for UG586.  Look at the User Interface section.

Visitor pedminacar
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Registered: ‎06-05-2019

Re: Help with DMA

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Hi,

I'm gonna try to use FIFO. Thank you for your help!

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Visitor pedminacar
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Registered: ‎06-05-2019

Re: Help with DMA

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I was thinking and realised I don't really need the FIFO, I can put the data directly in my design. But I have one doubt, is the write address of the AXI protocol the same address as the one of TLP source address? I mean, I have the following map in my head: My VHDL file with an algorithm, then the DMA IP, then the PCI, then the host. I am thinking that the DMA will send a TLP to host with an address, and the host answers with the data of that same address. When the DMA receives the data, it will redirect the data to my VHDL file. Now, I know that the AXI protocol have a address for read and an address to write. Is the write address the same as the previous TLP? And then the read address will be the same as the destination address of TLP?

Thank you

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Visitor pedminacar
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Registered: ‎06-05-2019

Re: Help with DMA

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One more question is how to write a descriptor so the DMA knows where to find the data? Is it in my aplication in the host? I would be very appreciate if someone provides a document with the instructions to make a descriptor. I can't find anything on the internet.

Thanks

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